Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-09-09
2001-04-24
Trinh, Michael (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S278000, C438S291000, C438S587000
Reexamination Certificate
active
06221723
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method of forming a semiconductor device, and more particularly to a method of setting multiple different threshold voltage levels to a plurality of cell transistor channel regions for a multiple-valued mask programmable read only memory in a reduced number of code selective ion-implantation processes.
In the mask programmable read only memory, ROM codes are decided in accordance with data supplied by the users. In order to decide the ROM code, it is necessary to carry out a plurality of code ion-implantation processes, wherein different mask patterns formed by photo-lithography processes are used to selectively ion-implant boron into selected cell transistor channel regions of the mask programmable read only memory. The selected, cell transistor channel regions having received boron implantation increase in threshold voltage level V
T
. The unselected cell transistor channel regions free of boron implantation remain unchanged in threshold voltage level V
T
. As a result of the plural code ion-implantation processes, the cell transistor channel regions have individually different threshold voltage levels. The difference in threshold voltage level of the cell transistor channel regions forms data. If two different threshold voltage levels are written into the cell transistor channel regions, this means that those cell transistor channel regions have binary digit data. If three or more different threshold voltage levels are written into the cell transistor channel regions, this means that those cell transistor channel regions have multiple valued data. In this case, the mask programmable read only memory is so called as a multiple-valued mask programmable read only memory.
FIG. 1
is a fragmentary plane view illustrative of arrays of cell transistor channel regions of a multiple-valued mask programmable read only memory.
The multiple-valued mask programmable read only memory has alternating alignments of a plurality of stripe-shaped n+-type buried regions
101
and
102
extending in a first horizontal direction and a plurality of rectangular-shaped p+-type isolation regions
200
which are aligned in the first horizontal direction so that each of the stripe-shaped p+-type isolation regions
200
isolates adjacent two of the stripe-shaped n+-type buried regions
101
and
102
. Each pair of the stripe-shaped n+-type buried regions
101
and
102
sandwiches the alignment in the first horizontal direction of stripe-shaped p+-type isolation regions
200
. The stripe-shaped n+-type buried regions
101
and
102
form source and drain regions of each cell transistor respectively. The stripe-shaped n+-type buried region
101
also serves as a ground line. The stripe-shaped n+-type buried region
102
also serves as a bit line.
The multiple-valued mask programmable read only memory further has a plurality of word lines
103
which extend in parallel to each other and in a second horizontal direction perpendicular to the first horizontal direction along which the stripe-shaped n+-type buried regions
101
and
102
extend. The word lines
103
extend cross over the stripe-shaped n+-type buried regions
101
and
102
. The word lines
103
also serve as gate electrodes. First, second and third square-shaped cell transistor regions “a”, “b” and “c” are represented by dotted lines. The rectangular-shaped p+-type isolation regions
200
isolates the first and second square-shaped cell transistor regions “a” and “b”. Each of cell transistor channel regions
104
is positioned under the word line
103
and is sandwiched between the rectangular-shaped p+-type isolation regions
200
in the first horizontal direction and also sandwiched between the stripe-shaped n+-type buried regions
101
and
102
. The threshold voltages of the cell transistor channel regions
104
are set to decide ROM-codes by boron-implantations carried out in accordance with the data supplied by the users.
FIGS. 2A through 2G
are fragmentary cross sectional elevation views illustrative of a plurality of sequential ion-implantation processes involved in a conventional method of setting multiple threshold voltage levels of cell transistor channel regions of the multiple-valued mask programmable read only memory. Four different threshold voltage levels of the cell transistor channel regions of the multiple-valued programmable read only memory are set by combined uses of code ion-implantations into a p-well region over a silicon substrate. The four different threshold voltage levels, for example, first, second, third and fourth threshold voltage levels V
T0
, V
T1
, V
T2
, and V
T3
, are set by first, second and third code ion-implantations into the individual cell transistor channel regions of the four-valued programmable read only memory in accordance with data from the user. The first threshold voltage level V
T0
is the lowest threshold voltage level. The second threshold voltage level V
T1
is the second lowest threshold voltage level. The third threshold voltage level V
T2
is the second highest threshold voltage level. The fourth threshold voltage level V
T3
is the highest threshold voltage level.
With reference to
FIG. 2A
, a p-well region
300
is formed over a silicon substrate. Field oxide films are selectively formed on the p-well region
300
over the silicon substrate to define an active region surrounded by the field oxide films. A gate oxide film
301
is formed on the active region of the p-well region
300
. Further, gate electrodes are formed on the surface of the gate oxide film
301
so that the gate electrode are aligned at a constant pitch, wherein only four gate electrodes, for example, first to fourth gate electrodes
302
a
,
302
b
,
302
c
and
302
d
are illustrated.
With reference to
FIG. 2B
, a photo-resist is applied on an entire surface of the silicon substrate for subsequent photo-lithography process to form a photo-resist pattern
303
over the filed oxide film so that the photo-resist pattern
303
has an opening positioned over the active region or the gate electrodes
302
a
,
302
b
,
302
c
and
302
d.
With reference to
FIG. 2C
, an ion-implantation of boron into an upper region of the p-well region
300
is carried out by use of the photo-resist pattern
300
and the gate electrodes
3
a
,
3
b
,
3
c
and
3
d
as masks, whereby p-type isolation regions
304
a
,
304
b
,
304
c
,
304
d
and
304
e
are formed in the upper region of the p-well region
300
and positioned under apertures between the gate electrodes
302
a
,
302
b
,
302
c
and
302
d
. This ion-implantation of boron is carried out at an ion-implantation energy of 20 KeV, and at a dose of about 1×10
13
cm
−2
. The formations of the p-type isolation regions
304
a
,
304
b
,
304
c
,
304
d
and
304
e
define first to fourth cell transistor channel regions
305
a
,
305
b
,
305
c
and
305
d
. The first cell transistor channel region
305
a
is defined between the first and second p-type isolation regions
304
a
and
304
b
and also is positioned under the first gate electrode
302
a
. The second cell transistor channel region
305
b
is defined between the second and third p-type isolation regions
304
b
and
304
c
and also is positioned under the second gate electrode
302
b
. The third cell transistor channel region
305
c
is defined between the third and fourth p-type isolation regions
304
c
and
304
d
and also is positioned under the third gate electrode
302
c
. The fourth cell transistor channel region
305
d
is defined between the fourth and fifth p-type isolation regions
304
d
and
304
e
and also is positioned under the fourth gate electrode
302
d
. The first, second, third and fourth cell transistor channel regions
305
a
,
305
b
,
305
c
and
305
d
have the first threshold voltage level V
T0
as the lowest threshold voltage level.
With reference to
FIG. 2D
, the used photo-resist pattern
303
is removed before a photo-resist pattern
306
NEC Corporation
Trinh Michael
Young & Thompson
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