Method of self-aligning a damascene gate structure to...

Details Method of self-aligning a damascene gate structure to... Method of self-aligning a damascene gate structure to...

2002-08-22

2004-03-30

Pert, Evan (Department: 2829)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S183000, C438S196000, C438S197000, C438S221000, C438S299000

Reexamination Certificate

active

06713335

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to self-align a damascene type gate structure to isolation regions.
(2) Description of Prior Art
Micro-miniaturization, or the ability to fabricate semiconductor devices comprised with sub-micron features, has been directly related to advances in photolithography. The use of more sophisticated exposure cameras as well as the use of more advanced photosensitive materials have allowed the desired sub-micron images to be defined in photoresist layers. The same photoresist layers comprised with the sub-micron images, are than used as an etch mask to allow the sub-micron images or features to be transferred to materials used for semiconductor device via anisotropic dry etching procedures. However the ability to correctly align or overlay overlying sub-micron features to underlying sub-micron features can still present problems.
The present invention will describe a novel process sequence in which a gate structure, and an underlying gate insulator layer, are formed, self-aligned to existing isolation regions. This novel process sequence employs only a single photolithographic procedure, and a single photolithographic mask or retide, to form the isolation regions, the subsequent self-aligned gate insulator layer and the gate structure. The gate structure and underlying gate insulator layer, can be formed via damascene procedures, with the gate insulator layer comprised of a high dielectric constant (high k) gate insulator layer. Prior arts such as: Ang et al, in U.S. Pat. No. 6,258,677 1; Rodder, in U.S. Pat. No. 6,261,887 B1; Hsieh et al, in U.S. Pat. No. 6,248,634; and Tsutsumi, in U.S. Pat. No. 5,789,792, describe methods of integrating gate structures with already formed isolation regions. However none of these prior arts describe the novel process sequence described in this present invention in which a damascene type gate structure and gate insulator layer are defined self-aligned to isolation regions.
SUMMARY OF THE INVENTION
It is an object of this invention to fabricate a semiconductor device in which the gate structure, and underlying gate insulator layer are self-aligned to isolation regions.
It is another object of this invention to define a damascene type, gate structure and gate insulator layer, self-aligned to isolation regions without the use of a photolithographic procedure for definition of the gate structures.
In accordance with the present invention a method of forming a gate structure and underlying gate insulator shape, self-aligned to isolation regions, is described. Silicon nitride shapes are formed on the top surface of both P well and N well regions located in top portions of a semiconductor substrate. After formation of the heavily doped source/drain regions, in portions of the P well and N well regions not covered by the silicon nitride shapes, silicon oxide spacers are formed on the sides of the silicon nitride shapes, overlying portions of the heavily doped source/drain regions. Photolithographic and dry etching procedures are then employed to form shallow trench shapes in portions of the semiconductor substrate located between the silicon nitride shapes, which are lined with the silicon oxide spacers. Filling of the shallow trench shapes with silicon oxide is followed by densification and planarization procedures resulting in shallow trench isolation (STI) structures, with bottom portions of the STI structures located in the P well and N well regions of the semiconductor substrate, while overlying top portions of the STI structures are located between the silicon nitride shapes. Selective removal of the silicon nitride shapes results in STI structures now comprised with, and widened by the addition of the remaining silicon oxide spacers. After formation of silicon nitride spacers on the sides of the STI structures, a high dielectric constant (high k) layer, and a conductive layer are deposited, followed by an etch back procedure resulting in a damascene type conductive gate structure and a high k gate insulator layer located between the silicon nitride spacers, which in turn are located on the sides of the exposed STI structures. Selective removal of the silicon nitride spacers allows the formation of lightly doped source/drain (LDD) regions, to be accomplished in the vacated space, with the LDD regions butting the heavily doped source/drain regions located under the STI regions. Refilling of the spaces created by removal of the silicon nitride spacers, with a silicon nitride—silicon oxide composite layer is followed by deposition of an interlevel dielectric (ILD) layer. Openings to the heavily doped source/drain regions in both P well and N well regions, are then accomplished in the ILD layer and in top portions of the STI structures, via selective dry etching procedures, using the silicon nitride component of the composite layer as a sidewall etch stop layer. Deposition of a metal layer, filling the openings, is followed by patterning procedures defining the desired metal contact and interconnect structures.


REFERENCES:
patent: 5789792 (1998-08-01), Tsutsumi
patent: 6248643 (2001-06-01), Hsieh et al.
patent: 6258677 (2001-07-01), Ang et al.
patent: 6261887 (2001-07-01), Rodder

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