Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-08-02
2002-08-13
Chaudhuri, Olik (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S688000
Reexamination Certificate
active
06432820
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for forming a metal wiring layer.
2. Description of the Related Art
As the integration density of semiconductor devices increases, it becomes necessary to introduce metal wiring layers having a multilayered wiring structure into the semiconductor circuits. Since metal wiring layers transmit electrical signals, it is necessary to use a material for the metal wiring layers, that has low electrical resistance and high reliability, and is economical. To meet these demands, aluminum is widely is used as the material of the metal wiring layers.
However, as line width of a circuit decreases, there are technical limits in applying conventional deposition techniques to form a metal wiring layer in a process for manufacturing a semiconductor device. Thus, a technique of burying either a contact hole connecting a lower conductive layer to an upper aluminum wiring layer or a via hole connecting a lower aluminum wiring layer to an upper aluminum wiring layer, by using a wiring material is considered to be very important to electrically interconnect the layers to each other.
To obtain superior electrical properties and burying characteristics when burying the contact hole or via hole (hereinafter, only the contact hole will be mentioned) with aluminum, a variety of processing techniques have been developed. In a deposition process for forming a metal wiring layer in the manufacture of a next generation memory device, in which the line width of a circuit is no greater than 0.25 &mgr;m, the aspect ratio of a contact hole is high, and thus it is quite improper to completely rely on a physical vapor deposition (PVD) process, such as sputtering. To overcome the problem of high aspect ratio of a contact hole, various studies have been conducted on processes for forming the aluminum wiring layer using a chemical vapor deposition (CVD) method, especially, a preferential metal deposition (PMD) method, which has superior step coverage characteristics, as compared to the PVD method, in which an aluminum film is formed within a contact hole using a CVD method and is deposited outside the contact hole using a PVD method. In the PMD method, to selectively form an aluminum film within a contact hole, a metal deposition prevention layer is formed on an interlayer dielectric layer pattern which defines the contact hole, thereby exposing only the inside of the contact hole, and then the aluminum film is formed within the contact hole using a CVD method.
In a conventional PMD method, to form the metal deposition prevention layer, a predetermined metal layer is formed on the interlayer dielectric layer pattern and then is exposed to atmosphere, thereby oxidizing the metal layer. The metal deposition prevention layer obtained by exposing the metal layer to atmosphere and inducing the generation of a natural aluminum oxide layer is used as an anti-nucleation layer for preventing deposition of the aluminum film introduced by a subsequent CVD process.
However, as described above, in the conventional PMD process, the metal layer is exposed to the atmosphere to generate a natural aluminum oxide layer, and thus the degree to which the natural aluminum oxide layer is formed varies depending on the exposure time. In other words, in the case of exposing the aluminum film after forming aluminum on the interlayer dielectric layer pattern, if the aluminum film is exposed to the atmosphere for a long time, the inside of the contact hole may be affected by natural oxidization. As a result, in the case of forming the aluminum film within the contact hole using a CVD method, the aluminum film may be not perfectly deposited at upper side walls of the contact hole near the entrance of the contact hole.
In addition, to obtain an oxide layer that is capable of sufficiently preventing metal deposition by taking advantage of a natural oxidation phenomenon, at least 2 hours of oxidation time is required. To perform a natural oxidation process introduced by exposing a metal layer to the atmosphere in the case of performing a metal wiring layer formation process using a cluster tool type equipment, a wafer should be taken out from the cluster tool type equipment in order to expose the wafer to the atmosphere and then returned into the equipment. At this time, it is impossible to maintain the original vacuum state of the equipment. To create a desired vacuum state again, a predetermined amount of time is necessary to exhaust the equipment of air. Therefore, a problem may arise in that the throughput of the process may be considerably lowered.
Also, in the case of forming the metal deposition prevention layer by taking advantage of the natural oxidation phenomenon introduced by exposure of a metal layer to the atmosphere, it is impossible to numerically control the process of forming a natural oxide layer, and thus it is difficult to ensure the reproducibility of the process. In addition, during the exposure of a metal layer to the atmosphere, the metal layer may be contaminated by unnecessary particles or a critical defect may occur. These problems may directly decrease the yield of semiconductor devices to be manufactured.
SUMMARY OF THE INVENTION
To address the above limitations, it is an object of the present invention to provide a method for forming a metal wiring layer of a semiconductor device, which is capable of ensuring the reproducibility of a process, preventing contamination caused by particles or occurrence of defects, and enhancing the throughput of the process.
Accordingly, to achieve the above object, there is provided a method for forming a metal wiring layer according to a first aspect of the present invention. An interlayer dielectric layer pattern defining a hole region is formed on a semiconductor substrate. A metal film is formed on the top surface of the interlayer dielectric layer pattern under vacuum so as to expose the inner side walls of the hole region. A metal deposition prevention layer is formed by oxidizing the metal film in an oxygen atmosphere in an airtight space the pressure of which is maintained below atmospheric pressure. A metal liner is selectively formed at the inner side walls of the exposed hole region. A metal layer is formed within the hole region defined by the metal liner and on the metal deposition prevention layer. The metal layer is reflowed by performing heat-treatment.
The hole region is one of a contact hole exposing one of a source/drain region and a conductive layer of a semiconductor substrate, a via hole, and a groove having a depth smaller than a thickness of the interlayer dielectric layer pattern.
Before the step of forming the metal film, the method for forming a metal wiring layer according to the first aspect of the present invention, may selectively further comprise: the steps of forming a resistant metal layer on the semiconductor substrate on which the interlayer dielectric layer pattern is formed; or forming a barrier metal layer on the resistant metal layer.
Also, the method for forming a metal wiring layer according to the first aspect of the present invention, may further comprise the step of heat-treating the barrier metal layer after the step of forming the barrier metal layer.
The step of forming the metal deposition prevention layer by oxidizing the metal film may be performed in an O
2
gas atmosphere or a mixed gas atmosphere of an oxygen-based gas and an inert gas.
The step of heat-treating the barrier metal layer may be performed at a temperature of 400-550° C.
The method for forming a metal wiring layer according to the first aspect of the present invention, may further comprise the step of moving the semiconductor substrate including the metal film into the airtight space between the step of forming the metal film and the step of forming the metal deposition prevention layer. The airtight space is formed in a reaction chamber which is capable of vacuum air exhaustion. Altern
Choi Gil-heyun
Kim Byung-hee
Lee Jong-myeong
Lee Myoung-bum
Chaudhuri Olik
Kielin Erik
Mills & Onello LLP
Samsung Electronics Co,. Ltd.
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