Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2001-02-26
2002-07-09
Zarabian, A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S201000
Reexamination Certificate
active
06418069
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention lies in the integrated technology field and relates, more specifically, to a method for repairing defective memory cells of an integrated memory.
Such a method is described in U.S. Pat. No. 5,410,687. There, individual memory cells of a memory are tested which are located at cross points of rows and columns. The memory has, for each column and each row, an error counter in which the errors detected for this column or row, respectively, are added together. After all memory cells have been checked, a repair of defective memory cells is effected by means of redundant column and row lines on the basis of the information stored in the error counters. The method described has the disadvantage that the error counters needed for its execution require a relatively large space.
U.S. Pat. No. 5,206,583 describes an integrated circuit which has separable connections (fuses) for a permanent programming of redundant elements. The integrated circuit also has reversibly programmable elements in the form of latches which are connected in parallel with the fuses and which are used for testing the reversible programming of the redundant elements.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a method of repairing defective memory cells of an integrated memory device which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this general kind, and wherein the necessary hardware components require the smallest possible area.
With the above and other objects in view there is provided, in accordance with the invention, a method of repairing defective memory cells of an integrated memory. The memory has memory cells arranged at cross points of row lines and column lines and reversibly programmable redundant lines including redundant row lines and redundant column lines. The method comprises the steps of:
successively testing the memory cells;
immediately upon detecting a defect of a memory cell being tested, replacing the respectively affected row line or column line by programming one of the redundant lines;
after a certain number of the redundant lines have been programmed, canceling a programming of a given one of the redundant lines upon detecting a further defect; and
programming the given redundant line for repairing a defect of another memory cell.
In other words, according to the novel testing method, the memory cells are successively checked. Immediately following the detection of a defect of the memory cell checked in each case, the row line affected or the column line affected is replaced by programming one of the redundant lines. After a certain number of the redundant lines has been programmed, the programming of at least one redundant line is canceled when a further defect is detected, and this redundant line is programmed for repairing a defect of another memory cell.
The column lines can be, for example, bit lines and the row lines can be, for example, word lines of the integrated memory. In other exemplary embodiments, the column lines can also be word lines and the word lines can be bit lines of the memory.
The method has the advantage that (in contrast with the above-noted U.S. Pat. No. 5,410,687) no error counters are required for each column line and row line to be checked since a defect is in each case repaired immediately after it has been detected. To achieve a certain optimization of the repair to be carried out, nevertheless, the programming of at least one of the redundant lines is canceled in dependence on the number of redundant lines already programmed previously so that this redundant line can then be used to repair a defect found later.
The reversible programming of the redundant lines can be done, for example, by means of reversibly programmable elements such as the latches described in U.S. Pat. No. 5,206,583. The repair method according to the invention is distinguished by an extremely small hardware expenditure so that it is particularly suitable for implementing a self-test and a self repair of the integrated memory to be repaired. This means that all components required for carrying out the repair method are components of the integrated memory or, respectively, are arranged in the same integrated circuit together with this memory. On the other hand, naturally, the method according to the invention can also be implemented in software or can also be performed by an external tester of the integrated memory.
In accordance with an added feature of the invention:
the memory cells are tested for defects row by row;
upon finding a defect of the memory cell being tested, the affected column line is replaced with one of the redundant column lines if a number of the programmed redundant column lines does not exceed a threshold value;
if the threshold value is exceeded, any programming of redundant column lines which has taken place due to defects having been found in the affected row line is canceled; and
the affected row line is replaced with one of the redundant row lines.
In accordance with an additional feature of the invention, the threshold value, i.e., the limit value for the number of redundant column lines to be programmed, is changed during the checking. This provides for an adaptation to the number of redundant column lines not yet programmed which still exists.
According to this first embodiment of the repair method, the memory cells are checked for defects row by row and, when a defect of the memory cell just checked is detected, the column line affected is replaced by a redundant column line if the number of programmed redundant column lines does not then exceed a limit value. When the limit value is exceeded, any programming of redundant column lines which has taken place on the basis of defects detected in the row line affected are canceled and the row line affected is replaced by one of the redundant row lines.
In this embodiment, a repair of detected defects in each case takes place perpendicularly to the direction of testing. This is because testing takes place row by row and replacement initially takes place column by column. It is only when the number of the redundant column lines already used exceeds the limit value that the preceding programming operations are at least partially canceled. However, it is only the programming operations of those redundant column lines which have been programmed on the basis of defects recognized in the relevant row line which are being canceled. Since the row line affected is then replaced by a redundant row line and the programming of redundant column lines which has taken place on the basis of row lines previously tested is not canceled, all defects detected are repaired in the manner described within a single test run through the memory cells if there are sufficient redundant lines.
In accordance with an alternative feature of the invention, the novel method provides for the following steps:
testing the memory cells, beginning at a start address;
once all redundant lines have been programmed, canceling the programming of one of the redundant lines if a further defect is found;
retesting the memory cells, beginning at the start address;
if, during the retesting step, a defect is found, with an address before the further defect, reversing the canceling of the programming of the corresponding redundant line;
subsequently repeating the three preceding method steps with respect to the step of canceling the programming of another one of the redundant lines;
if, after canceling the programming of one of the redundant lines, during the subsequent testing of the memory cells, no defect is found with an address before the further defect, repairing the further defect with the redundant line that has become available due to the canceling of its programming.
In other words, the memory cells are tested beginning with a start address. Once all redundant lines have been programmed, the programming of one of the redundant lines is canceled when another defect is detected. The memory cells are then
Schamberger Florian
Schneider Helmut
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Stemer Werner H.
Zarabian A.
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