Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1999-09-24
2002-07-02
Lane, Jack A. (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S005000, C365S222000
Reexamination Certificate
active
06415353
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related to semiconductor memories, especially dynamic random access memory (DRAM) and static random access memory (SRAM). In particular, the present invention relates to a method and apparatus of handling refresh operations in a semiconductor memory such that the refresh operations do not interfere with external access operations.
DISCUSSION OF RELATED ART
A conventional DRAM memory cell, which consists of one transistor and one capacitor, is significantly smaller than a conventional SRAM cell, which consists of 4 to 6 transistors. However, data stored in a DRAM cell must be periodically refreshed, while the data stored in an SRAM cell has no such requirement. Each refresh operation of a DRAM cell consumes memory bandwidth. For example, the cycle time of a 100 MHz DRAM array is 10 nsec. In this DRAM array, each external access takes 10 nsec, and each refresh access takes at least 10 nsec. Because an external access and a refresh access can be initiated at the same time, the DRAM array must be able to handle both within the allowable access cycle time so as to prevent the refresh access from interfering with the external access. This limits the minimum external access cycle time to be no less than 20 nsec, with 10 nsec for handling the external access and 10 nsec for handling the refresh access. This is true even though the refresh accesses are performed, on average, at a frequency of 62.5 kHz. As a result, the maximum accessing frequency of the DRAM array must be less than or equal to 50 MHz. Thus, a 100 Mhz DRAM memory array is required to create a device capable of operating at 50 MHz. This is simply not economical.
Previous attempts to use DRAM cells in SRAM applications have been of limited success for various reasons. For example, one such DRAM device has required an external signal to control refresh operations. (See, 131,072-Word by 8-Bit CMOS Pseudo Static RAM, Toshiba Integrated Circuit Technical Data (1996).) Moreover, external accesses to this DRAM device are delayed during the memory refresh operations. As a result, the refresh operations are not transparent and the resulting DRAM device cannot be fully compatible with an SRAM device.
In another prior art scheme, a high-speed SRAM cache is used with a relatively slow DRAM array to speed up the average access time of the memory device. (See, U.S. Pat. No. 5,559,750 by Katsumi Dosaka et al, and “Data Sheet of 16 Mbit Enhanced SDRAM Family 4M×4, 2M×8, 1M×16” by Enhanced Memory Systems Inc., 1997.) The actual access time of the device varies depending on the cache hit rate. Circuitry is provided to refresh the DRAM cells. However, the refresh operation is not transparent to external accesses. That is, the refresh operations affect the memory access time. Consequently, the device cannot meet the requirement of total deterministic random access time.
Other prior art schemes use multi-banking to reduce the average access time of a DRAM device. Examples of multi-banking schemes are described in “Data sheet, MD904 To MD920, Multi-bank DRAM (MDRAM) 128K×32 to 656K×32” by MoSys Inc., 1996, and in “An Access-Sequence Control Scheme to Enhance Random-Access Performance of Embedded DRAM's” by Kazushige Ayukawa et al, IEEE JSSC, vol. 33, No. 5, May 1998, pp. 800-806. These multi-banking schemes do not allow an individual memory bank to delay a refresh cycle.
Another prior art scheme uses a read buffer and a write buffer to take advantage of the sequential or burst nature of an external access. An example of such a prior art scheme is described in U.S. Pat. No. 5,659,515, entitled “Semiconductor Memory Device Capable of Refresh Operation in Burst Model” by R. Matsuo and T. Wada. In this scheme, a burst access allows a register to handle the sequential accesses of a transaction while the memory array is being refreshed. However, this scheme does not allow consecutive random accesses. For example, the memory cannot handle a random access per clock cycle.
Another prior art scheme that attempts to completely hide refresh operations in a DRAM cell includes the scheme described in U.S. Pat. No. 5,642,320, entitled “Self-Refreshable Dual Port Dynamic CAM Cell and Dynamic CAM Cell Array Refreshing Circuit”, by H. S. Jang. In this scheme, a second port is added to each of the dynamic memory cells so that refresh can be performed at one port while a normal access is carried out at the other port. The added port essentially doubles the access bandwidth of the memory cell, but at the expense of additional silicon area.
Accordingly, it would be desirable to have a memory device that utilizes area-efficient DRAM cells, and handles the refresh of the DRAM cells in a manner that is completely transparent to an accessing memory client external to the memory device. That is, it would be desirable for the refresh operations to be successfully performed without relying on unused external access time. Stated another way, it would be desirable to have a memory device that allows the use of DRAM cells or other refreshable memory cells for building SRAM compatible devices or other compatible memory devices that do not require refresh.
SUMMARY
Accordingly, the present invention provides a memory device that includes a plurality of memory cells that must be periodically refreshed in order to retain data values, and a control circuit for accessing and refreshing the memory cells. In one embodiment, the memory cells are DRAM cells. The control circuit controls the accessing and refreshing of the memory cells such that the refreshing of the memory cells does not interfere with any external access of the memory cells.
The memory cells are arranged in a plurality of independently controlled memory banks. Thus, read, write and refresh operations are independently controlled within each bank. Each of the memory banks is coupled in parallel to a read buffer, such that data read from any one of the memory banks is provided to the read buffer. Each of the memory banks is further coupled in parallel to a write buffer, such that data written to any of the memory banks can be provided from the write buffer.
The control circuit includes an SRAM cache, which has the same configuration as each of the memory banks. A cache read buffer is coupled between an output port of the SRAM cache and the write buffer, thereby facilitating the transfer of data from the SRAM cache to the memory banks. similarly, a cache write buffer is coupled between an input port of the SRAM cache and the read buffer, thereby facilitating the transfer of data from the memory banks to the SRAM cache. The cache read buffer and the cache write buffer are further coupled to an external data bus. The SRAM cache provides an interface between the external data bus and the memory banks. The SRAM cache implements a write-back policy, such that all write data is initially written to the SRAM cache before being written to the memory banks, and all read data provided to the external data bus is stored in the SRAM cache. In one embodiment, the SRAM cache is configured as a direct map cache. The SRAM cache is selected to have a capacity sufficient to ensure that each of the memory banks is refreshed properly within a predetermined refresh period. That is, even under the worst case cache-thrashing conditions, the required refresh operations will always be performed without delaying any external accesses to the memory device.
In one embodiment, the cache write-back policy is carried out as follows. First, a current access address received on the external data bus is compared with a cached address stored in the SRAM cache to determine whether a cache miss or a cache hit occurs. When a cache hit occurs, the requested data is either read from the SRAM cache (for a read access) or written to the SRAM cache (for a write access). Thus, the memory banks are not accessed when a cache hit occurs. Refresh operations can therefore be performed within the memory banks when a cache hit occurs, when a refresh request is pending. Because the memory
Hoffman E. Eric
Lane Jack A.
Law Offices of Bever, Hoffman & Harms, LLP
Monolithic System Technology, Inc.
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