Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2001-05-08
2002-03-12
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S720000, C438S723000, C438S742000
Reexamination Certificate
active
06355566
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the field of semiconductor assembly, and more particularly to a method for removing surface defects from oxide or other materials.
BACKGROUND OF THE INVENTION
A structure commonly formed during the manufacture of semiconductor devices such as microprocessors, memory devices, and logic devices includes a plug or stud manufactured from polycrystalline silicon (poly) or metal such as tungsten. For purposes of illustration only, this disclosure discusses the formation of a plug from poly. The plug typically contacts a doped layer in a semiconductor substrate or contacts some other underlying structure. To manufacture the plug, a masked dielectric layer is formed over the underlying structure and an etch is completed to form a hole in the dielectric which exposes the underlying structure to which contact is to be made. A blanket poly layer is deposited over the dielectric layer which fills the hole in the dielectric layer and contacts the underlying structure. The poly is then removed from a planar surface of the dielectric, typically using a chemical mechanical polishing (CMP) process which leaves the plug formed within the dielectric layer.
Ideally, the process described above would leave a poly plug having an upper surface which is flush with the upper level of the dielectric layer. CMP results in a sufficiently-flush plug but it is not a particularly clean or uniform process and, in practice, can damage surface structures. Previous dry etches are cleaner than CMP but can result in a plug having a concave upper surface which is recessed into the dielectric layer. It is difficult to form a reliable electrical connection to a recessed plug with a subsequently formed layer such as metal.
Another problem with the process described above results from surface defects in the dielectric, such as surface scratches, cracks, or other voids or recesses formed during manufacture of the dielectric layer. During conductor formation these surface defects are filled with poly which remains in the void after CMP removal of the poly from the surface of the dielectric. The poly remaining in the voids, also referred to as “stringers,” can form a short between other conductive structures such as between two or more plugs or between other structures such as metal lines which are subsequently formed.
A method for forming a conductive plug or stud which reduces or eliminates the problems described above would be desirable.
SUMMARY OF THE INVENTION
The present invention provides a new method that reduces problems associated with the manufacture of semiconductor devices, particularly problems resulting in a concave profile of a conductive plug and resulting in stringers or other undesirable conductive fragments. In accordance with one embodiment of the invention a dielectric layer is formed having a desired hole therein and further having an undesired void therein. A blanket conductive layer is formed over the dielectric layer and a first etch is performed which clears a portion of the conductive layer. The first etch removes the conductive layer at a substantially faster rate than it removes the dielectric layer. Subsequently, a second etch is performed which removes the conductive layer and the dielectric layer at about the same rate. At least a portion of the dielectric layer is removed during this etch to remove the void and any conductive layer within the void.
The first etch quickly clears the conductive layer and ideally stops just as the underlying dielectric layer is exposed. The second etch removes the dielectric layer and the conductive layer ideally at the same rate to form a conductive plug having an upper surface which is flush with an upper surface of the dielectric layer. It would be possible to perform the second etch only and omit the first etch, but the chemistry required for the second etch removes the conductive layer at a much slower rate and thus would decrease manufacturing throughput.
Objects and advantages will become apparent to those skilled in the art from the following detailed description read in conjunction with the appended claims and the drawings attached hereto.
REFERENCES:
patent: 4708767 (1987-11-01), Bril
patent: 4824802 (1989-04-01), Brown et al.
patent: 4879257 (1989-11-01), Patrick
patent: 4917759 (1990-04-01), Fisher et al.
patent: 5164330 (1992-11-01), Davis et al.
patent: 5260232 (1993-11-01), Muroyama et al.
patent: 5585308 (1996-12-01), Sardella
patent: 5753547 (1998-05-01), Ying
Blalock Guy
Howard Bradley J.
Jost Mark E.
Niebling John F.
Zarneke David A
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