Etching a substrate: processes – Gas phase etching of substrate – Irradiating – ion implanting – alloying – diffusing – or...
Reexamination Certificate
1999-12-14
2002-07-30
Gulakowski, Randy (Department: 1746)
Etching a substrate: processes
Gas phase etching of substrate
Irradiating, ion implanting, alloying, diffusing, or...
C216S067000, C134S022100, C438S424000, C438S428000, C438S433000, C438S778000, C438S783000, C438S789000
Reexamination Certificate
active
06426015
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a method for reducing, during processing of semiconductors, excessive etching-away of portions of glass-like layers of insulation, the insulation typically being a fused compound of silicon, boron, and other elements. Such defective etching is caused by elevated concentrations of boron where the insulation interfaces with or touches portions of a semiconductor device, namely, conductive elements of the device and the insulated substrate of a chip upon which the device is formed.
BACKGROUND OF THE INVENTION
In recent years the density of semiconductor devices has increased greatly. There are now commercially available dynamic random access memories (DRAMS) with as many as 256 megabit memory elements on a single small chip of silicon. There will be available in the near future devices with as many as a gigabit of active elements per chip. Such high density has resulted in certain problems, not only in design, but in the manufacturing of the devices.
Among the steps to which a silicon wafer is subjected in the course of processing into devices, such as high density DRAMs, is the step of applying to the devices a layer or layers of high temperature insulation. Typically, a thin glass-like layer containing silicon and other elements is used as the insulation. In the case of high density DRAMS, for example, the spaces separating one memory cell from another on the chip can be as narrow as a small fraction of a micron in DRAMs now in production. The depth perpendicular to the face of the chip of such narrow spaces can be great enough that it becomes difficult to fully fill them with insulation free of voids.
A conventional way of applying insulation to semiconductor devices is to deposit silicon dioxide (SiO
2
) using chemical vapor deposition (CVD) onto the devices within a reaction chamber containing a gaseous mixture of tetraethylorthosilicate (TEOS) and ozone. As the film grows over the topographical surface, having spaces or gaps between elements of devices, the film thus fills the gaps. However, due to the nature of the reaction mechanism, the top surfaces of these gaps tend to receive more incoming reactant and thus higher growth rates, compared to the bottom portions. Therefore, voids tend to develop during the CVD process because of the greater depth-to-width ratio of the spaces in high-density semiconductor devices (e.g. gigabit DRAMS). To eliminate this difficulty TEOS is mixed in suitable proportion with triethylborate (TEB) and triethylphosphate (TEPO), as is well known in the art. The voids in insulation previously encountered are eliminated by the more “flowable” mixture of silicon, phosphorus and boron. But such an insulating layer in a thin zone where it touches or interfaces with bare surfaces of semiconductor elements (e.g., memory cells) of a device or with a dielectric layer, contains a much higher concentration of boron than contained elsewhere in the insulation. Thereafter when portions of insulation are selectively etched away using buffered hydrofluoric acid (BHP), as conventionally used in the art, the acid too aggressively attacks the boron-rich zones of the insulation at the interface surfaces. This condition results in undesirable under cutting (or excessive etching away) of these boron-rich zones. This in turn exposes or lays bare conductive portions of elements of the device. When metal conductors are subsequently applied to the etched devices in a metalizing step, electrical short-circuits can occur. This clearly is an unacceptable condition.
It is desirable to substantially eliminating such boron-rich zones in the insulation layers, and minimizes defective etching of these layers and the electrical short-circuits resulting therefrom.
SUMMARY OF THE INVENTION
The present invention is directed to a method for substantially eliminating zones of elevated boron concentrations (termed hereinafter “boron-spikes”) in insulation layers where they touch or interface with surfaces of elements (e.g., memory cells) and the substrate of a semiconductor device. Substantial elimination of “boron-spikes” reduces defective etching of such insulation layers prior to application to the device of metalized layers (electrical conductors) and possible electrical short-circuits.
Before applying insulation to the surfaces of semiconductors within a reaction chamber, it has been customary prior to the present invention to clean the chamber of residues of chemicals left over from a previous processing step. Then a semiconductor wafer is placed in the chamber and insulation is formed via CVD reaction of tetraethylorthosilicate (TEOS), triethylborate (TEB), triethylphosphate (TEPO) and ozone, as is well known in the art.
In accordance with the present invention, a clean reaction chamber, before a semiconductor wafer is placed into it, is “seasoned”, or pre-conditioned by a step of introducing into the chamber the same general kind of insulating compound (i.e., a mixture of TEOS, TEB and TEPO) as also applied later to semiconductors on a wafer, and under similar conditions of times, temperatures, pressures and concentrations.
By way of example, a clean reaction chamber (without a wafer) is “seasoned” in a specific embodiment of the invention by the following conditioning treatment. This comprises flowing into the chamber at ambient temperature and a pressure of about 400 Torr and above, the following mixture of gasses: TEOS at 800 milligrams per minute (mgm), while keeping other gasses flowing at normal rates, e.g. TEB=120 mgm, TEPO=50 mgm, and O
3=
4000 sccm −12 wt. %. For convenience, we can pick similar flow rates as the actual deposition conditions. The total “seasoning” time is about 60 sec. Such a “seasoning” step tends to passivate the inner walls of the chamber and reduce surface absorption of the reactants during deposition, and leaves on the walls a thin oxide coating to a suitable thickness (e.g., a faction of a micron). Thereafter a semiconductor wafer is inserted into the now “seasoned” chamber and insulation is applied to the devices on the wafer by a closely similar process using materials, times, and conditions such as utilized in the previous chamber “seasoning” treatment. The insulation deposited onto the devices is reflowed by heating the devices to a suitably high temperature, as is well known. In this way boron-spikes in the insulating layers formed on the semiconductor devices are substantially eliminated and resulting defects in subsequent etching of the layers are essentially avoided. Of course, exact times, chemical proportions, pressures, etc. in forming insulating layers on semiconductor devices will depend on the needs of the particular devices then being insulated.
(Claim
1
) Viewed from a first aspect, the present invention is directed to a method for reducing boron concentrations in an insulating layer containing silicon, boron and other elements where the layer interfaces with surfaces of a semiconductor wafer. The method comprises the steps of: seasoning a reaction chamber by flowing into it a mixture of gasses comprising silicon, boron, phosphorous, and in predetermined proportions under set conditions of time, pressure, temperature and flow rates to passivate the inner walls and surfaces of the chamber with a thin oxide deposition seasoning coating; and placing a semiconductor wafer in the chamber and covering it with an insulating layer having a composition similar to the seasoning coating such that boron spiking is reduced and subsequent etching of selected portions of the insulating layer does not expose conductive surfaces of devices formed in and/or on the semiconductive wafer which are not desired to be exposed.
(Claim
5
) Viewed from a second aspect, the present invention is directed to a method for reducing boron concentrations in and defective etching resulting therefrom of an insulating layer containing boron and phosphorus doped silicon oxide where the layer interfaces with a surfaces of a surface of a semiconductor wafer. The method comprises the steps of:
Campana Francimar
Xia Li-Qun
Yieh Ellie
Gulakowski Randy
Kornakov M.
Townsend and Townsend and Crew
LandOfFree
Method of reducing undesired etching of insulation due to... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of reducing undesired etching of insulation due to..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of reducing undesired etching of insulation due to... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2884247