Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-07-29
2003-10-28
Le, D (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S599000, C438S622000, C438S668000, C438S155000, C257S531000, C257S516000
Reexamination Certificate
active
06638844
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to fabrication of semiconductor devices, and more specifically to methods of fabricating RFCMOS components.
BACKGROUND OF THE INVENTION
As shown in
FIG. 1
, conventional radio frequency complimentary metal-oxide semiconductor (RFCMOS) components utilize conductive metal/polysilicon and silicide shields for inductors and a triple-well approach for transistor noise reduction. That is, a gate electrode
12
is formed over P-substrate
10
and underlying P-well
18
, N-well
20
and standard P-well
19
. Sidewall spacers
14
are formed over the side walls of gate electrode
12
with source/drain implants
22
extending therefrom within substrate
10
. A resist protect oxide (RPO) layer
16
is formed over the substrate
10
adjacent gate electrode
12
.
Shallow trench isolation (STI) structures
24
,
26
are formed within substrate
10
to electrically isolate gate electrode
12
with STI structure
26
formed beneath inductor coils
30
. An interlevel dielectric (ILD) layer or intermetal dielectric (IMD) layer
28
is formed over gate electrode
12
and RPO layer
16
.
Inductor coils
30
are formed over ILD/IMD layer
28
with corresponding field plate coils
32
formed under inductor coils
30
within ILD/IMD layer
28
. Inductor coils
30
/field plate coils
32
are formed over STI structure
26
, for example.
FIG. 2
is a plan view of
FIG. 1
taken along line
2
—
2
showing the coiled nature of inductor coil(s)
30
.
Although substrate coupling and noise are reduced, they are not sufficiently reduced to desired levels.
U.S. Pat. No. 5,520,299 to Belcher et al. describes a backside trench etch process.
U.S. Pat. No. 6,287,932 B2 to Forbes et al. describes a spiral inductor process with insulating layers.
U.S. Pat. No. 6,100,199 to Joshi et al. describes a method for forming embedded thermal conductors for semiconductor chips using a backside trench etch process.
U.S. Pat. No. 6,303,423 B1 to Lin describes a method for forming high performance system-on-chip using post passivation process. High quality electrical components, such as inductors, capacitors or resistors, are formed on a layer of passivation or on the surface of a thick layer of polymer.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide an improved method of fabricating RFCMOS components.
It is another object of the present invention to provide a method to fabricate on-chip inductors with minimal substrate coupling.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a substrate having a frontside and a backside is provided. One or more RFCMOS components are formed over the substrate. One or more isolation structures are formed within the substrate proximate the one or more RFCOMS components. The backside of the substrate is etched to form respective trenches within the substrate and over at least the one or more isolation structures. The respective trenches are filled with dielectric material whereby the substrate coupling and noise for the one or more RFCMOS components are reduced.
REFERENCES:
patent: 5520299 (1996-05-01), Belcher et al.
patent: 6100199 (2000-08-01), Joshi et al.
patent: 6287932 (2001-09-01), Forbes et al.
patent: 6303423 (2001-10-01), Lin
patent: 6448168 (2002-09-01), Rao et al.
Chan Lap
Chu Sanford
Hwei Chit
Verma Purakh Raj
Chartered Semiconductor Manufacturing Ltd.
Le D
Pike Rosemary L. S.
Saile George O.
Stanton Stephen G.
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