Method of reducing stress migration in integrated circuits

Details Method of reducing stress migration in integrated circuits Method of reducing stress migration in integrated circuits

2005-02-15

2005-02-15

Whitehead, Jr., Carl (Department: 2829)

Semiconductor device manufacturing: process

Radiation or energy treatment modifying properties of...

Reexamination Certificate

active

06855648

ABSTRACT:
A method for reducing stress migration in the copper interconnect line is set forth. In accordance with the method, two anneal steps take place: The first step is at low temperature and of relatively short duration (e.g., about 25-300° C., and about 10 seconds-10 hours). After the first anneal, the wafer is cooled to room temperature. The second step is performed after the cooling step; a higher anneal temperature and longer time duration is needed to enhance performance.

REFERENCES:
patent: 5166095 (1992-11-01), Hwang
patent: 6258220 (2001-07-01), Dordi et al.
patent: 6508920 (2003-01-01), Ritzdorf et al.
patent: 6511718 (2003-01-01), Paz de Araujo et al.

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