Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2001-03-10
2003-12-30
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S585000, C438S199000, C438S287000, C438S655000
Reexamination Certificate
active
06670263
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of reducing polysilicon depletion and modulating resistance in a polysilicon gate electrode, by depositing the polysilicon controllably so as to vary in a predetermined manner the grain size of the polysilicon through its thickness. In particular, according to this invention, a method is provided for producing a polysilicon structure in which the crystalline composition of the polysilicon is varied in a controlled manner during deposition, which results in the structure having a controllably varied crystalline composition as a function of depth.
BACKGROUND OF THE INVENTION
Field effect transistors (FETs) and doped polysilicon resistors are common elements in solid state circuits. Gate conductors are formed by the deposition of crystalline polysilicon which is subsequently doped and, in many instances, must have a predetermined electrical resistance. Furthermore, it is important that polysilicon electrical depletion adjacent to an interface with dielectric be minimized in order to improve transistor performance.
U.S. Pat. No. 6,017,810, to Furukawa et al., titled “Process for Fabricating Field Effect Transistor with a Self-Aligned Gate to Device Isolation”, suggests a method for forming a gate conductor from an N
+
or P
+
type doped polycrystalline silicon on an insulating layer, but does not teach variation of crystal grain size in controlled manner.
U.S. Pat. No. 5,766,989, to Maegawa et al., titled “Method for Forming Polycrystalline Thin Film and Method for Fabricating Thin Film Transistor”, suggests a method of forming a polysilicon semiconductor thin film, which, in part, contains microcrystals that serve as crystal nuclei for polycrystallization on an insulating substrate. The film is polycrystallized by laser annealing to generate crystals all of substantially the same size. This reference discusses prior art in which excimer laser radiation is employed to generate polycrystalline layers having crystals of different size where the variation occurs laterally, i.e., in a direction perpendicular to a direction of the thickness of the polysilicon.
U.S. Pat. No. 5,346,850, lo Kaschmitter et al., titled “Crystallization and Doping of Silicon on Low Temperature Plastic”, suggests the use of short-pulsed high energy processing of an amorphous silicon layer to crystallize the same.
U.S. Pat. No. 5,164,338, to Graeger et al., titled “method of Manufacturing a Polycrystalline Semiconductor Resistance Layer of Silicon on a Silicon body and Silicon Pressure Sensor Having Such a Resistance Layer,” suggests a method of manufacturing a polycrystalline semiconductor resistance layer over an insulating layer, in which the polysilicon is first applied as a continuous nearly amorphous silicon layer. This layer is thermally processed to promote the epitaxial growth of additional polycrystalline silicon thereon.
It is considered that none of the known prior art teaches a method in which a crystalline polysilicon deposit has a controlled crystal size varying with depth.
SUMMARY OF THE INVENTION
This invention provides a method of forming a crystalline polysilicon deposit in which crystal grain size is controllably varied with depth of the deposit in a simple and versatile fashion.
This invention also makes possible a structure in which a deposit of crystalline polysilicon is formed to have a predetermined variation in crystal grain size as a function of depth.
Accordingly, in a first aspect of this invention there is provided a method of forming a polycrystalline silicon structure in which crystal grain size varies as a function of depth, control being exercised to vary at least one of temperature, pressure and flow rate of a silane gas while depositing silicon therefrom, to thereby control the crystal grain size as a function of depth in the deposited silicon structure.
In another aspect of this invention, there is provided a method of forming a polysilicon gate electrode structure on a gate dielectric, which includes the steps of depositing on the gate dielectric silicon crystals of substantially a first size and, thereafter, contiguously with the crystals of the first depositing additional silicon crystals of substantially a second size.
In a related aspect of this invention, there is provided a CMOS transistor structure which includes a gate conductor formed on a gate dielectric. The gate conductor comprises a multi-region polycrystalline silicon in which a first region adjacent the dielectric has crystals of a first grain size, and a second region formed contiguously over the first region has crystals of a second grain size.
In yet another related aspect of this invention, there is provided a dopes poly -Si resistor structure which includes a multi-region polycrystalline silicon structure formed over a dielectric.
These and other aspects and advantages of the present invention will be understood from the following detailed description with reference lo the appended figures.
REFERENCES:
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patent: 4929570 (1990-05-01), Howell
patent: 5164338 (1992-11-01), Graeger et al.
patent: 5346850 (1994-09-01), Kaschmitter et al.
patent: 5441904 (1995-08-01), Kim et al.
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patent: 5751050 (1998-05-01), Ishikawa et al.
patent: 5766989 (1998-06-01), Maegawa et al.
patent: 6008077 (1999-12-01), Maeda
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Ballantine Arne W.
Chan Kevin K.
Gilbert Jeffrey D.
Houlihan Kevin M.
Miles Glen L.
Connolly Bove & Lodge & Hutz LLP
Niebling John F.
Pompey Ron
Sabo William D.
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