Method of reducing overetch during the formation of a semiconduc

Details Method of reducing overetch during the formation of a semiconduc Method of reducing overetch during the formation of a semiconduc

1998-05-20

2000-11-28

Niebling, John F.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

438586, 438592, 438738, 438743, 438744, H01L 2128

Patent

active

06153501&

ABSTRACT:
A method of forming a transistor for a semiconductor device from a semiconductor wafer comprises forming a first nitride layer over the front and back of the wafer, and forming a second nitride layer over the front and back of the wafer and over the first nitride layer. A first resist layer is formed over the front of the wafer and at least a portion of the second nitride layer over the front of the wafer is exposed. The first and second nitride layers are removed from the back of the wafer while, simultaneously, at least a portion of the exposed portion of the second nitride layer over the front of the wafer is removed. Next, a second layer of resist is formed leaving at least a portion of the first nitride layer exposed. Finally, the exposed portion of the first nitride layer is etched.

REFERENCES:
patent: 3288662 (1966-11-01), Weisberg
patent: 3740280 (1973-06-01), Ronen
patent: 3939555 (1976-02-01), Jantsch et al.
patent: 4152824 (1979-05-01), Gonsiovowski
patent: 4256829 (1981-03-01), Daniel
patent: 4450021 (1984-05-01), Batra et al.
patent: 4523372 (1985-06-01), Balda et al.
patent: 4666555 (1987-05-01), Tsang
patent: 4758525 (1988-07-01), Kido et al.
patent: 4789648 (1988-12-01), Chou et al.
patent: 4853345 (1989-08-01), Himelick
patent: 4966870 (1990-10-01), Barber et al.
patent: 4999317 (1991-03-01), Lu et al.
patent: 5022958 (1991-06-01), Farreau et al.
patent: 5084416 (1992-01-01), Ozaki et al.
patent: 5202291 (1993-04-01), Charvat et al.
patent: 5286674 (1994-02-01), Roth et al.
patent: 5310454 (1994-05-01), Ohiwa et al.
patent: 5321211 (1994-06-01), Haslam et al.
patent: 5426073 (1995-06-01), Imaoka et al.
patent: 5498570 (1996-03-01), Becker
patent: 5753565 (1998-05-01), Becker
patent: 5846443 (1998-12-01), Abraham
S. Wolf et al, "Silicon Processing For the VLSI Era vol. 1" Lattice Press, 1986, pp. 168-171, 187-193.
Penkunas et al., "Simultaneous Exposure of Photoresist on Both Sides of a wafer", Western Electric Technical Digest No. 35, Jul. 1974, pp. 47-48.
Co-pending application: "Method Of Reducing Overetch During The Formation Of A Semiconductor Device," Serial No. 08/728,007, Docket #96-0339.00 filed Oct. 9, 1996.

Affiliated with

Also associated with

Rating

Method of reducing overetch during the formation of a semiconduc does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of reducing overetch during the formation of a semiconduc, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of reducing overetch during the formation of a semiconduc will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1725241