Method of reducing notching during reactive ion etching

Details Method of reducing notching during reactive ion etching Method of reducing notching during reactive ion etching

2001-12-26

2004-04-13

Kunemund, Robert (Department: 1765)

Etching a substrate: processes

Gas phase etching of substrate

Etching inorganic substrate

C216S039000, C216S040000, C438S706000, C438S719000, C438S723000

Reexamination Certificate

active

06719918

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of reducing notching during reactive ion etching (RIE), and more particularly, to a method of reducing notching in a lower portion of a silicon layer when RIE is performed to pass through the silicon layer on a sequentially-stacked structure of the silicon layer, an insulating layer and a silicon substrate.
2. Description of the Related Art
A reactive ion etching (RIE) method has been generally used to pattern a silicon structure. However, when RIE is performed to pass through a silicon layer on a multi-layered structure of the silicon layer, an insulating layer and a silicon substrate, the silicon layer is prone to be overetched due to a microloading effect. For instance, as shown in
FIG. 1
, a region having a large aperture
36
in which the etching rate is fast is overetched while a region having a small aperture
34
in which the etching rate is slow is etched to be passed through. As a result, the surface of an insulating layer
20
is charged with electricity by an etching ion which reacts to form an electric potential on the insulating layer
20
. Due to the electric potential, the etching ion is reflected from the insulating layer
20
, which causes unnecessary lateral etching in a lower portion of a silicon layer
30
. The lateral etching, i.e., notching
32
, makes a structure thinner and further, the surface of the structure irregular, thereby deteriorating the mechanical and electrical characteristics.
To prevent such notching, there was an attempt to form a metal layer on an insulating layer so that an etching ion can be discharged therefrom. However, this method is inconvenient because it requires additional deposition of a metal layer and anodic bonding.
SUMMERY OF THE INVENTION
To solve the above problem, it is an object of the present invention to provide a method of remarkably reducing notching occurring in a lower portion of a silicon layer when RIE is performed to pass through the silicon layer on a sequentially-stacked structure of the silicon layer, an insulating layer and a silicon substrate.
To accomplish the above object, there is provided a method of reducing notching occurring when RIE is performed to pass through a silicon layer in a multi-layered structure in which the silicon layer, an insulating layer and a silicon substrate are sequentially deposited according to the present invention. The method includes the steps of: (a) forming an insulating layer on a silicon substrate; (b) forming trenches on the insulating layer to expose the silicon substrate; (c) forming a silicon layer on the insulating layer to fill the trenches; and (d) patterning the silicon layer to form first etch regions, which pass through the silicon layer, to include the trenches.
It is preferable that in step (d) the silicon layer between the trenches is patterned to form second etch regions which are narrower than the first etch regions.
Also, it is preferable that in step (d) silicon filled in the trenches is removed to expose the silicon substrate.


REFERENCES:
patent: 6071822 (2000-06-01), Donohue et al.
patent: 6180486 (2001-01-01), Leobandung et al.
patent: 6187685 (2001-02-01), Hopkins et al.
patent: 6245635 (2001-06-01), Lee
patent: 6261966 (2001-07-01), Li et al.

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