Method of reducing junction capacitance of source/drain region

Details Method of reducing junction capacitance of source/drain region Method of reducing junction capacitance of source/drain region

1998-10-16

2002-05-07

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S301000, C438S307000

Reexamination Certificate

active

06383883

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 87113022, filed Aug. 7, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a method of reducing junction capacitance of a source/drain region, and more particularly, to a method of using double implantation to reduce junction capacitance of a source/drain region.
2. Description of the Related Art
As the dimension of a metal-oxide semiconductor (MOS) device shrinks, the operation speed of the transistor becomes faster due to the shortened channel length. However, as the channel is shortened toward a certain limit, a hot electron effect is induced to a cause malfunction or operation failure. The structure of a lightly doped drain (LDD) has been widely used to solve the short channel effect.
FIG. 1A
to
FIG. 1C
are schematic cross sectional views showing a method of forming a source/drain region. In
FIG. 1A
, using thermal oxidation, a gate oxide layer
20
is formed on a substrate
10
. A polysilicon layer and a tungsten silicide layer are formed on the gate oxide layer
20
. Using photolithography and etching process, a gate
12
is defined. In
FIG. 1B
, a lightly doping process is performed to form a light doped drain structure. Arsenic ions
30
are implanted into the substrate with the gate
12
as a mask. The substrate
10
is disposed into a furnace for annealing, so that the surface atomic structure which has been damaged during ion implantation is rearranged. A lightly doped drain region
16
is thus formed. In
FIG. 1C
, a silicon oxide layer is formed to cover the substrate
10
and the gate
12
. A part of the silicon oxide layer is removed by etch back to form a spacer on a side wall
14
of the gate
12
. Using the gate
12
and the spacer
14
as masks, a heavily doped region
18
, that is, a source/drain region is formed by implanting arsenic ions
30
' with a higher concentration into the substrate
10
deeper than the LDD region
16
.
A depletion region is formed at the interface between the source/drain region and the substrate due to the different potentials. The depletion region is electrically neutral. Therefore, the depletion region is equivalent to a dielectric layer between the electrodes (source/drain region) and the substrate. As a consequence, a junction capacitance is induced. The junction capacitance is closely related to the width of the depletion region, and the width of the depletion region depends on the concentration gradient of the implanted ions in the substrate. The distribution profile of implanted ions formed by the above conventional method is relatively abrupt to form a steep depletion region, therefore, a larger junction capacitance is caused to deteriorate the device operation.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a method of forming a method of reducing the junction capacitance of a source/drain region. In addition to implanting arsenic ions to form the source/drain region, another step of implanting phosphorus ions into the source/drain region is performed. The arsenic ions distribution gradient is thus declined. Consequently, the junction capacitance is reduced, and the operation speed of device is enhanced.
To achieve the above-mentioned objects and advantages, a method of reducing junction capacitance is provided. A gate oxide layer is formed on a substrate. A polysilicon layer and a tungsten slicide layer are formed on the gate oxide layer. Using photolithography and etching process, a gate is defined. Using the gate as a mask, a lightly doped drain region is formed by implanting arsenic ions with a light concentration into the substrate. A thermal process is performed for arsenic ions diffusion. An insulation layer is formed to cover the substrate and the gate. Using dry etching to remove a part of the insulation, a spacer is formed on a side wall of the gate. Using the gate and the spacer as masks, arsenic ions with higher concentration is implanted deeper into the substrate. A thermal process is performed for arsenic ion diffusion. Another arsenic ion implantation is further performed to form a source/drain region.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


REFERENCES:
patent: 5648286 (1997-07-01), Gardner et al.
patent: 5753556 (1998-05-01), Katada et al.
patent: 6004849 (1999-12-01), Gardner et al.
patent: 6107149 (2000-09-01), Wu et al.

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