Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1996-09-30
1998-12-01
Niebling, John
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438306, 438585, 438586, 438589, H01L 21336
Patent
active
058438270
ABSTRACT:
A method of suppressing damage to gate dielectrics by reducing the electrical field across the gate dielectric during plasma etching, photoresist stripping, or plasma assisted deposition of the overlying conductor to be etched. Openings in the gate oxide in the vicinity of the gates to be formed place the two conductive layers in contact with each other before the gates are formed and allows for the underlying conductive layer (usually the substrate) to be exposed to the plasma as the overlying unmasked conductive layer (usually polysilicon) is etched away. Preferably, the layer to be etched is deposited to be in contact with the underlying layer at the openings. This technique is applicable to integrated capacitor structures and other susceptible structures with a dielectric layer between two conductors.
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Gregor Richard William
Leung Chung Wai
Gurley Lynne A.
Lucent Technologies - Inc.
MacLellan Scott W.
Niebling John
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