Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-10-15
2004-08-24
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S236000, C438S309000, C438S312000
Reexamination Certificate
active
06780702
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of reducing device parasitic capacitance using underneath crystallographically selective wet etching. In more detail, it relates to a technology of reducing parasitic capacitance simply by using underneath crystallographically selective wet etching and thereby providing a self-alignable, structurally-stable device without resistance increase.
2. Description of the Related Art
With a recent innovative development in wireless communication technology, demand for an ultrafast broadband communication network using a millimeter wave is being increased. A local multi-point distribution system (LMDS), which transmits voices, video signals, and/or digital signals simultaneously with 1.3 GHz bandwidth within a 2~7 Km radius range using 28 GHz “Ka-band”, can be a good example of this kind of network system.
For constructing an ultrafast broadband communication network as described above, it is important to develop an extremely high frequency device that can be operated in extremely high frequency band.
In a heterojunction bipolar transistor (HBT), it is very important to reduce base-collector parasitic capacitance for an ultrafast operation. Therefore, various efforts have been made for reducing base-collector parasitic capacitance such as a collector ion-implantation, a selective growing of sub-collector layer, a side overetching of collector layer, and so on.
In case of ion-implantation, however, a deep ion-implantation is required for isolation effect being occurred. And for selectively growing an epi-layer, it requires various additional processing steps to increase the overall processing complexity.
And in case of using a side etching, side etching is being carried out after locating a device in parallel to a crystallographical direction of <
010
> or <
001
>, with which side etching can be performed comparatively well. Or else, i.e. in case of a direction parallel to a general <
011
>, an overetching is being carried out due to the bad side-etching characteristic.
SUMMARY OF THE INVENTION
The present invention is proposed to solve the problems of the prior art mentioned above. It is therefore the object of the present invention to provide a manufacturing method, comprising simple processing steps, of a device that is structurally stable, has a small parasitic capacitance without the increase of contact resistance, and can be self-aligned.
To achieve the object mentioned above, the present invention presents a manufacturing method of a device for reducing parasitic capacitance on the laminated structure of an InP/InGaAs double heterojunction bipolar transistor (DHBT) comprising: a first process of alternately laminating a first and a second sub-collector InGaAs layers/a base InGaAs layer/an emitter InGaAs layer and an etch stop InP layer/a collector InP layer/a first and a second emitter InP layers on an InP substrate by an epitaxy method; a second process of depositing an emitter metal layer thereon and thereafter etching the emitter InGaAs layer and the first and second emitter InP layers in sequence, for a base metal to be self-alignable, to expose the upper surface of the base InGaAs layer; a third process of defining a photo resistor (PR) thereon for protecting the emitter region and thereafter etching the base InGaAs layer; a fourth process of etching the collector InP layer with using the base InGaAs layer as a mask to expose the upper surface of the second sub-collector InGaAs layer; a fifth process of selectively side-etching the second sub-collector InGaAs layer to expose the bottom surface of the collector InP layer where void region is formed; a sixth process of performing an anisotropic selective etching on the bottom surface of the collector InP layer, which contributes to parasitic capacitance, with using the second sub-collector InGaAs layer as a mask and on the surface of the etch stop InP layer simultaneously to expose the upper surface of the first sub-collector InGaAs layer; and a seventh process of eliminating the photo resistor (PR) and thereafter depositing a metal layer to form a base- and a collector-metal layers.
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Yang Kyoung Hoon
Yoon Myoung Hoon
Harness & Dickey & Pierce P.L.C.
Kennedy Jennifer M.
Korea Advanced Institute of Science and Technology
Niebling John F.
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