Method of reducing charge loss for nonvolatile memory

Details Method of reducing charge loss for nonvolatile memory Method of reducing charge loss for nonvolatile memory

2003-02-12

2004-06-08

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

By reaction with substrate

Reexamination Certificate

active

06746968

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to the semiconductor manufacturing process, and particularly to a method of reducing charge loss for a nonvolatile memory cell.
2. Description of the Related Art
Nonvolatile memory cell arrays such as EPROMs, FLASH EPROMs and EEPROMs have gained widespread acceptance in the industry. Nonvolatile memory cells do not require periodic refresh pulses needed by the capacitive storage elements of conventional one-device dynamic random access memory (DRAM) cells. This presents an appreciable power saving. Because they rely upon charge injection/removal to establish the stored logic state, the write cycles of nonvolatile memory cells are appreciably longer than those of DRAM's.
It has been observed that there are data retention problems in nonvolatile memory cell arrays. It has been postulated that the poor data retention is due to mobile ions such as Na+, K+, or the like that approach the floating gate in the nonvolatile memory cell and cause the charge on the floating gate to be lost. For example, an inter-layer dielectric (ILD) layer (made up of a high dielectric reflowable material such as phosphosilicate glass or borophosphosilicate glass) is formed on the wafer. The manufacturing process for forming the ILD layer, such as deposition, photolithography and etching, causes the mobile ions to be introduced to approach the floating gate in the nonvolatile memory cell, seriously affecting device reliability.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method for reducing charge loss for a nonvolatile memory cell to enhance reliability.
The method comprises the subsequent steps. First, a semiconductor substrate having a semiconductor device thereon is provided. Next, a dielectric layer is formed on the entire surface of the semiconductor substrate. Then, thermal treatment is performed in an atmosphere containing a reactive gas, and the reactive gas reacts with free ions remaining from the semiconductor substrate during manufacturing processes. Finally, a metal layer is formed on the dielectric layer.
According to the present invention, a passivation is further formed on the metal layer after formation thereof. The thermal treatment can be performed after forming the dielectric layer. Also, the thermal treatment can be formed after forming the passivation.
According to the present invention., step of performing thermal treatment can be replaced by introducing anions to react with cations remaining in the semiconductor. Step of performing thermal treatment can also be replaced by introducing a gas to react with dangling bonds of the whole semiconductor substrate.


REFERENCES:
patent: 6071784 (2000-06-01), Mehta et al.
patent: 6635943 (2003-10-01), Hui et al.
patent: 2003/0124873 (2003-07-01), Xing et al.

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