Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – By reaction with substrate
Reexamination Certificate
2002-04-25
2004-01-20
Thompson, Craig A. (Department: 2813)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
By reaction with substrate
Reexamination Certificate
active
06680261
ABSTRACT:
CROSS-REFERENCES TO RELATED APPLICATIONS
This application claims priority from R.O.C. Patent Application No. 090110463, filed May 2, 2001, the entire disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
FIG. 1
shows a cross-section of a general N-type power IC, the fabrication method of which is described herein. An oxide layer is formed on the N-type substrate
10
. A patterned photoresist layer is formed on the oxide layer to define an active region. P type dopants are implanted into the substrate
10
. After the drive-in process is proceeded, a P
−
type body
12
is formed in the active region. Then the photoresist layer is removed, and another photoresist layer is formed to define the gate area. Etching is conducted to form a trench
14
in the substrate
10
. After removing the photoresist layer and before forming a gate oxide layer
16
, a sacrificial layer is formed on the surface of the trench with an oxidation process conducted in a furnace. The sacrificial layer is removed. The gate oxide layer
16
is formed and a polysilicon layer acting as a gate
18
is formed in the trench. A patterned photoresist layer is then formed to define source/drain regions, and an implantation and RTA are sequentially performed to form the N
+
type source
20
at one side of the gate
18
. A BPSG layer
22
is deposited with a contact window therein, and P type dopants are implanted to form a P
+
type region
24
.
The oxidation process of the sacrificial oxide layer, formed before forming the gate oxide layer
16
, is given here.
Flow rate
Flow rate
Temperature
of N
2
of O
2
Required time
Step 1
900° C.
6
sccm
0
sccm
Step 2
900° C.
9
sccm
0
sccm
Step 3
900° C.
12
sccm
0.6
sccm
10 min
Step 4
Ramp up 5° C./min
12
sccm
0.6
sccm
Step 5
1150° C.
12
sccm
0.6
sccm
10 min
Step 6
1150° C.
0
sccm
12
sccm
5 min
Step 7
1150° C.
0
sccm
12
sccm
21 min
Step 8
1150° C.
0
sccm
12
sccm
5 min
Step 9
1150° C.
12
sccm
0
sccm
10 min
Step 10
Ramp down 3° C./min
12
sccm
0
sccm
Step 11
900° C.
9
sccm
0
sccm
Step 12
900° C.
6
sccm
0
sccm
The main oxidation steps are steps
6
~
8
after the furnace temperature reaches the oxidation temperature. In these oxidation steps, the flow rate of O
2
increases and reaches 12 sccm, and the flow of N
2
is interrupted. However, after analyzing the electric properties of the power IC, it is found that the threshold voltage of the power IC is too low and the difference of standard error is very large. This is because the boron is outgassing in these main oxidation steps and the impurities in the environment diffuse into the sacrificial oxide layer to induce dislocation in the substrate. Therefore, the concentration of boron near the surface of the trench is non-uniform. Furthermore, the location of the wafer in the furnace affects the threshold voltage of the power ICs so that the threshold voltage of the power ICs cannot be effectively controlled in the demanded range, so the power ICs belong to a different batch.
BRIEF SUMMARY OF THE INVENTION
Embodiments of the present invention are directed to a method of reducing boron outgassing at trench power IC's oxidation process for the sacrificial oxide layer whereby the threshold voltage of the power ICs can be improved and the yield of the product can be enhanced.
It is another feature of the present invention to prevent the impurities in the environment from diffusing into the sacrificial oxide layer, and the dislocation in the substrate can thus be reduced.
Yet another feature of the invention is to provide a new oxidation process for sacrificial oxide layer, so the threshold voltage of the power ICs can be controlled in the demanded range, no matter to which batch the power ICs belong and no matter in which zone the wafer is located in the furnace.
An aspect of the present invention is directed to a method of reducing boron outgassing at a trench of a trenched substrate of a power IC during an oxidation process for a sacrificial oxide layer. The method comprises placing the trenched substrate in a furnace; raising a temperature of the furnace to the oxidation temperature; and introducing nitrogen and oxygen into the furnace for main oxidation when the temperature of the furnace reaches the oxidation temperature. The nitrogen is sufficient in concentration in the furnace at the oxidation temperature to reduce boron outgassing at the trench.
In some embodiments, the oxidation temperature is about 1150° C. The nitrogen comprises N2. The flow rate of the nitrogen is about 8-20 sccm. Transdichloroethylene (TLC) is introduced into the furnace during the main oxidation after the temperature in the furnace reaches the oxidation temperature. The TLC is introduced after flow rates of the nitrogen and oxygen for the main oxidation are stable. For example, the TLC may be introduced at about 5 minutes after the nitrogen and oxygen for the main oxidation are introduced into the furnace to reach stable flow rates.
In specific embodiments, prior to raising the temperature of the furnace to the oxidation temperature, the furnace is prepared by introducing nitrogen into the furnace at a preparation flow rate which is sufficiently high to make the furnace near a saturated vapor pressure. The temperature of the furnace is ramped up to the oxidation temperature after preparing the furnace. After the temperature in the furnace is ramped up to the oxidation temperature and prior to introducing the nitrogen and oxygen into the furnace for main oxidation, the furnace is stabilized by maintaining the flow rate of the nitrogen at the preparation flow rates. Preparing the furnace may comprise introducing oxygen into the furnace at a preparation flow rate which is substantially lower than the flow rate of the oxygen during the main oxidation. Stabilizing the furnace may comprise maintaining the flow rate of the oxygen at the preparation flow rate. The preparation flow rate of the nitrogen may be about 12-18 sccm. A silicon nitride layer is formed during the main oxidation.
Another aspect of the present invention is directed to a method of reducing boron outgassing at a trench of a trenched substrate of a power IC during an oxidation process for a sacrificial oxide layer. The method comprises placing the trenched substrate in a furnace; preparing the furnace by introducing nitrogen into the furnace at a preparation flow rate which is sufficient to make the furnace near a saturated vapor pressure; ramping up a temperature of the furnace to an oxidation temperature while maintaining the flow rate of the nitrogen into the furnace at the preparation flow rate to make the furnace near the saturated vapor pressure; stabilizing the furnace by maintaining temperature of the furnace at the oxidation temperature and maintaining the flow rate of the nitrogen at the preparation flow rate to make the furnace near the saturated vapor pressure; and performing main oxidation of the trenched substrate by introducing nitrogen into the furnace at a main oxidation flow rate and introducing oxygen into the furnace at a sufficient flow rate for main oxidation.
In some embodiments, the preparation flow rate of nitrogen is about 12-18 sccm. The oxidation temperature is about 1150° C. The main oxidation flow rate of nitrogen is about 8-20 sccm. The flow rate of oxygen during the main oxidation is about 12 sccm. TLC may be introduced into the furnace during the main oxidation, after the flow rates of the nitrogen and oxygen for main oxidation are stable, until substantially all impurities are trapped. A silicon nitride layer is formed during the main oxidation.
In accordance with another aspect of the invention, a power IC comprises a substrate, and a gate structure overlying a silicon nitride layer formed in a trench of the substrate during main oxidation of the substrate.
REFERENCES:
patent: 6040216 (2000-03-01), Sung
patent: 6498079 (2002-12-01), Bryant et al.
Coating for Ultra High Voltage Pyrex Viewports to Prevent Boron Outgassing, IBM Tech. Disclosure Bulletin, Oct. 1994, Vol 37, No. 10, pp. 457-458.
Chen Jen-Te
Jaw Kou-Liang
Tseng Mao-Song
Yang Kou-Wei
Mosel Vitelic Inc.
Thompson Craig A.
Townsend and Townsend / and Crew LLP
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