Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1980-07-14
1982-11-02
Hecker, Stuart N.
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
365185, G11C 700
Patent
active
043576850
ABSTRACT:
A nonvolatile memory of the electrically alterable kind comprises an orthogonal array of cells each including a floating-gate IGFET and an enhancement IGFET in series. For the programming or the reading of a selected cell, lying at the intersection of a row and a column of the array, a common gate lead for all the enhancement IGFETs of the row and a common drain lead for all the enhancement IGFETs of the column are energized with voltage dependent on the desired kind of operation. To write a bit in a cell, its floating gate is progressively charged in a succession of steps separated by reading operations to check on the conduction threshold of the cell; the charging ends when that threshold reaches a predetermined storage level. To cancel a written bit, the floating gate is progressively discharged in a succession of steps again separated by reading operations; the discharging is terminated when the conduction threshold reaches a predetermined cancellation level. The width and/or the amplitude of a voltage pulse applied to an accessible gate of the floating-gate IGFET during the successive charging or discharging steps may be increased after each reading step in which the desired level is not attained.
REFERENCES:
patent: 3825946 (1974-07-01), Bentchkowsky
patent: 4149270 (1979-04-01), Cricchi et al.
patent: 4181980 (1980-01-01), McCoy
Corda Giuseppe
Daniele Vincenzo
Magrucci Aldo
Torelli Guido
Hecker Stuart N.
Ross Karl F.
SGS-ATES Componenti Elettronici S.p.A.
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