Method of production of semiconductor device

Details Method of production of semiconductor device Method of production of semiconductor device

2001-05-18

2002-02-05

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S310000, C438S323000, C438S302000, C438S235000

Reexamination Certificate

active

06344384

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of production of a semiconductor device; and, more particularly relates to a method of production of a semiconductor device having a BiCMOS transistor.
2. Description of the Related Art
Along with the increasingly small size and lighter weight of electronic equipment and the reduction of power consumption in recent years, there has been growing demand for higher integration and greater miniaturization of semiconductor devices. Therefore, there has been development of a bipolar CMOS (Bi-CMOS) combining a CMOS having the characteristics of low power consumption and high integration and a bipolar transistor having the characteristics of a strong drive force and high speed.
FIG. 13
is a sectional view of a BiCMOS transistor produced by a method of production of the related art.
As shown in
FIG. 13
, an n-type epitaxial layer
2
is formed on a p-type semiconductor substrate
1
, and an element isolation insulating film
3
is formed by a LOCOS technique on a surface of the n-type epitaxial layer
2
.
In an npn bipolar transistor formation region, an n-type collector burying region
4
is formed below the n-type epitaxial layer
2
forming an n-type collector region, and a selective-ion-implantation-of-collector (SIC) region
17
for increasing the concentration of impurity directly below a base is formed above the n-type collector burying region
4
.
An intrinsic base region
15
containing a p-type impurity and an external base region
16
for taking out a base containing a p-type impurity of a higher concentration than that in the intrinsic base region
15
and reduced in resistance are formed connected on the surface of the n-type epitaxial layer
2
.
A silicon oxide film
33
is formed on the p-type base regions (
15
and
16
). Emitter polycrystalline silicon
24
is formed in an opening
33
a
formed in the silicon oxide film
33
and on the silicon oxide film
33
. An n-type emitter region
25
is formed on the surface of the intrinsic base region
15
below the emitter polycrystalline silicon
24
.
Also, an n-type collector plug region
6
and an n-type collector take-out region
6
a
are formed on a part of the n-type epitaxial layer
2
on the n-type collector burying region
4
over the p-type base regions (
15
and
16
).
An n-type isolation region
5
for isolation from the p-type semiconductor substrate
1
is formed on a pMOS transistor formation region. Further, an n-type well
7
is formed in the n-type epitaxial layer
2
. Further, a p-type well
8
is formed in the nMOS transistor region.
In the pMOS and the nMOS transistor formation regions, source/drain regions (
12
and
14
) having LDD regions (
11
and
13
) are formed on the surfaces of the n-type well
7
and the p-type well
8
, respectively.
Also, gate electrodes (
22
and
23
) are formed between the source/drain regions (
12
and
14
) via the gate oxide films (
31
a
and
31
b
). Sidewall insulating films (
32
a
and
32
b
) are formed on the side portions of the gate electrodes (
22
and
23
).
A silicon oxide film
33
is formed covering the entire surfaces of the gate electrodes (
22
and
23
). An interlayer insulating film
34
is formed covering the entire surfaces of the transistors, contact holes (
41
,
42
,
43
,
44
,
45
,
46
, and
47
) reaching the source/drain regions (
12
and
14
) of the pMOS and nMOS transistors, the external base region
16
and an emitter electrode
24
of the npn bipolar transistor. A collector take-out region
6
a
is formed in the silicon oxide film
33
and the interlayer insulating film
34
. Interconnection layers (
51
,
52
,
53
,
54
,
55
,
56
, and
57
) are formed inside and over the contact holes.
An example of a method of production of the semiconductor device having the above configuration will be explained next.
First, as shown in
FIG. 14A
, for example, a p-type silicon semiconductor substrate
1
is oxidized by thermal oxidation to form an oxide film on the surface. On the upper surface of the oxide film, a resist film R
1
of a pattern having openings at the npn bipolar transistor formation region and the pMOS transistor formation region on the above silicon semiconductor substrate
1
is formed by lithography.
Then, the oxide film is patterned by using the resist film R
1
as a mask, so as to form an oxide film
36
having openings at the npn bipolar transistor formation region and the pMOS transistor formation region.
Next, as shown in
FIG. 14B
, the resist film R
1
is removed and antimony is diffused in the silicon semiconductor substrate
1
through the openings formed in the above oxide film
36
by thermal diffusion using a solid source of antimony oxide (Sb
2
O
3
) so as to form, for example, an n-type collector burying region
4
and an n-type isolation region
5
for isolation from the p-type semiconductor substrate
1
.
Next, as shown in
FIG. 15C
, the oxide film
36
is removed by, for example, wet etching, and then an n-type epitaxial layer
2
is formed on the silicon semiconductor substrate
1
by epitaxial growth.
Next, as shown in
FIG. 15D
, an element isolation insulating film
3
is formed on the n-type epitaxial layer
2
by a LOCOS process.
In the process of forming the element isolation insulating film
3
, for example, a silicon oxide film
3
a
is formed by thermal oxidation on the surface of the n-type epitaxial layer
2
, a not illustrated silicon nitride film is formed on regions other than the element isolation insulating film formation region on the silicon oxide film
3
a
and the surface of the n-type epitaxial layer
2
is thermally oxidized using the silicon nitride film as an oxidation resistant mask to form the element isolation insulating film
3
. Then, the silicon nitride film is removed by etching.
Next, as shown in
FIG. 16E
, a resist film R
2
having an opening at a region for forming an n-type collector plug region on the npn bipolar transistor formation region is formed. The resist film R
2
is used as a mask and, for example, the n-type impurity phosphorus is implanted, so as to form an n-type collector plug region
6
connected to the n-type collector burying region
4
on the n-type epitaxial layer
2
. Then, the resist film R
2
is removed.
Next, as shown in
FIG. 16F
, a resist film R
3
having an opening at the pMOS transistor formation region is formed by lithography on the n-type epitaxial layer
2
. An n-type impurity, for example, phosphorus, is implanted to form an n-type well
7
. Then, the resist film
3
is removed.
Next, as shown in
FIG. 17G
, a resist film R
4
having openings at an nMOS transistor formation region and a part of the element isolation region between the nMOS and pMOS transistor and npn bipolar transistor formation regions is formed on the n-type epitaxial layer
2
by lithography. A p-type impurity boron is then, for example, implanted to form a p-type well using the element isolation region.
Next, as shown in
FIG. 17H
, the resist film R
4
is removed. Then, the oxide film
3
a
is removed for example by wet etching, and a gate oxide film
31
is formed, for example, by thermal oxidation.
Next, as shown in
FIG. 18I
, gate electrodes (
22
and
23
) are formed on the nMOS and pMOS transistor formation regions.
Next, as shown in
FIG. 18J
, a resist film R
5
having an opening at the pMOS formation region is formed by lithography. The resist film R
5
is used as a mask for ion implantation of a p-type impurity, for example, boron difluoride (BF
2+
) to form a p-type LDD region
11
in the n-type wells
7
on the two sides of the gate electrode
22
. Then the resist film R
5
is removed.
Next, as shown in
FIG. 19K
, a resist film R
6
having an opening at the nMOS transistor formation region is formed by lithography. The resist film R
6
is used as a mask for implantation of an n-type impurity, for example, arsenic (As
+
) to form an n-type LDD region
13
in the p-type wells
8
on the two sides of the gate
23
. Then, the resist film R
6
is removed.
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