Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-05-25
2001-08-28
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06281071
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device, particularly a semiconductor integrated circuit memory device, and more particularly to structure which is effective when applied to a semiconductor integrated circuit device having dynamic random access memories (DRAMs), and methods for the production thereof. The present invention is further directed to a semiconductor integrated circuit device having a capacitor element, particularly a semiconductor integrated circuit memory device, such as a DRAM, having a stacked capacitor element, and methods of production thereof.
The present invention is further directed to wiring techniques having applicability in connection with various devices, including in connection with semiconductor integrated circuit devices, particularly semiconductor integrated circuit memory devices such as DRAMs.
Each of the memory cells constituting a DRAM includes a memory cell selecting MISFET and a capacitor element for storing information, such capacitor element being connected in series to one semiconductor region of the MISFET. The gate electrode of the memory cell selecting MISFET is connected to a word line which extends in the row direction so that the MISFET is controlled through this word line. The other semiconductor region of the memory cell selecting MISFET is connected to a data line which extends in the column direction.
Attempts are continuously being made, with respect to this type of DRAM, to increase its integration density, for the purpose of increasing the memory capacity, and therefore there is a tendency for the memory cell sizes to shrink. When the memory cell sizes are reduced, the size (area) of the capacitor elements, for storing the information, is also reduced which results in a decrease in the capacity of such capacitor elements for storing charges which constitute information. As the charge storing capacity decreases, the effect of minority carriers generated due to &agr;-particles increases, so that so-called soft errors are likely to occur. This occurrence of soft errors is particularly a problem in DRAMs having high integration density, such as 1 Mbit or more.
In view of this problem of soft errors generated due to &agr;-particles, stacked capacitor elements (STCs) have been adopted as information storage capacitor elements of the memory cells of DRAMs. A stacked capacitor element includes a first electrode layer, a dielectric film and a second electrode layer, which are successively stacked on a semiconductor substrate. The first electrode layer is formed in such a manner that, after memory cell selecting MISFETs of the memory cells have been formed, when part of the first electrode layer of the stacked capacitor elements is connected to one semiconductor region of the corresponding MISFET, another part thereof is extended above the gate electrode of the corresponding memory cell selecting MISFET. The first electrode layer is formed from a polycrystalline silicon film having an impurity (such as P or As, for example) introduced therein, for the purpose of lowering the resistance value of the polycrystalline silicon. The dielectric film is defined by a silicon oxide film formed by oxidizing the surface of the polycrystalline silicon film constituting the first electrode layer. The second electrode layer is formed integrally with the second electrode layers of other adjacent memory cells, thus providing a common plate electrode (as the second electrode layer). The second electrode layer is formed from a polycrystalline silicon film like that of the first electrode layer.
The aforementioned memory cell selecting MISFET of the memory cell is constructed into an n-channel type. This MISFET has its shape specified by the element insulating isolating film and a p-type channel stopper region, and is electrically isolated from the elements of other regions.
There is connected a data line with the other semiconductor region of the memory cell selecting MISFET of each memory cell in the array, such data line being connected to such other semiconductor region through an intermediate conducting layer which is formed in the same fabrication step as the first electrode layer of the storage capacitor element. Since this intermediate conducting layer is connected in self-alignment with the other semiconductor region, the data line is connected in self-alignment with the other semiconductor region even if a masking displacement is caused at the fabrication steps of the intermediate conducting layer and the data line.
Information stored in each memory cell of the DRAM is input through the above-described data line to a sense amplifier of a peripheral circuit, where it is amplified, and the amplified information is then output to a common data line through a Y-switch. The Y-switch is controlled by a column decoder circuit (Y-decoder circuit) through a Y-select signal line. The Y-select signal line is formed from the same conductive layer as that for the above-described data line and extends in the same column direction as the data line.
The memory cell comprising the above-described stacked capacitor elements has the advantage that incidence of soft errors can be reduced because such capacitor elements do not use the semiconductor substrate in which minority carriers are generated due to &agr;-particles incident thereon. In addition, the stacked capacitor element enables areas of the first and second electrode layers to be increased in the heightwise direction (direction extending perpendicular to the semiconductor substrate) by making use of the stepped configuration of the memory cell selecting MISFET. Due to such increased size, an increase in the capacity of storing charge which constitutes information is achieved, so that it is further possible to reduce soft errors.
The data lines of the DRAMs, mentioned previously, consist of an aluminum wiring having a small specific resistivity. An element for reducing electromigration and stress migration is added to the aluminum wiring forming the data line. For example, copper (Cu) is generally used as such element for reducing electromigration and stress migration; however, palladium (Pd) or titanium (Ti) can also be used as such element. In addition, silicon or the like has also been added to the aluminum wiring, in addition to the element(s) discussed above, in order to prevent an aluminum spike. Thus, a common wiring for the data line is an aluminum-copper-silicon wiring.
The aluminum wiring technique of a DRAM is described, for example, in “Nikkei Micro-Devices”, May Issue, 1987, pgs. 16-31, Special Issue No. 1, published by Nikkei-McGraw-Hill Co.
It should also be noted that a DRAM in which each memory cell includes a stacked capacitor element is described, for example, in Japanese Patent Laid-Open No. 183952/1986. The contents of this Japanese patent laid-open application are incorporated in their entirety herein.
SUMMARY OF THE INVENTION
Problems Found and Addressed by the Inventors
In attempting to develop a DRAM having increased capacity, the present inventors have found various problems in the above-described prior art structure, and in the methods of forming such structure.
A. In connection with a first aspect of the present invention, the inventors have found that when the information storage capacitor of the stacked structure is formed after the memory cell selecting MISFET has been formed, the source and drain region of the MISFET being formed by ion implantation at a relative high implantation flux of or above 10
15
atoms/cm
2
(providing a high impurity concentration region of or above 10
20
atoms/cm
3
), crystal defects are often caused in the principal surface portion of the semiconductor substrate (for example, a well region formed in the substrate) due to such ion implantation. Such crystal defects cannot be satisfactorily removed by annealing at a later step in the manufacturing process. Due to such defects, charges stored in the stacked capacitor element leak to the substrate, so that the information retention charact
Asano Isamu
Hiraiwa Atsushi
Horiuchi Mitsuaki
Kaneko Hiroko
Murata Jun
Antonelli Terry Stout & Kraus LLP
Hiatchi Ltd.
Tsai Jey
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