Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-03-25
2002-07-16
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S211000, C438S258000
Reexamination Certificate
active
06420222
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a structure of a high withstand voltage MOS transistor that is manufactured through a process of forming two polycrystalline silicon layers, a structure of a semiconductor device utilizing the high withstand voltage MOS transistor, and methods of manufacturing the same.
Conventionally, the process given hereinbelow has been utilized for forming DDD (Double-Diffused Drain) type MOS transistors and other types of MOS transistors by using two polycrystalline silicon layers on a semiconductor substrate.
First, a device isolating film
24
and an oxidized film
25
are formed on a silicon substrate
23
by a known technique, as shown in FIG.
3
A.
Then, as shown in
FIG. 3B
, after forming first polycrystalline silicon film by a known technique, the film is patterned and etch-removed to form a lower electrode
26
for a capacitance element. Then, formed are an insulating oxidized film
27
(a) on the lower electrode
26
and a gate oxidized film
27
(b) by thermal oxidation, as shown in FIG.
3
C. Then, a second polycrystalline silicon film is formed by a known technique as shown in
FIG. 3D
, and thereafter patterned and removed by etching to form an upper electrode
28
(
a
) for a capacitance element and a gate electrode
28
(
b
) for a transistor. Then, as shown in
FIG. 3E
, a photoresist material
29
is patterned by a known technique to selectively form by a known technique an impurity layer
30
(
a
) for a DDD at a transistor region to be formed with a DDD structure.
Then, as shown in
FIG. 3F
, a DDD diffusion layer
30
(
b
) is formed by a thermal diffusion process in order to obtain a diffusion width so that the impurity layer
30
(
a
) can function as a DDD. Then, as shown in
FIG. 3G
, source and drain layers
31
are formed in the transistor region by a known technique to thereby forming a DDD transistor and a capacitance element or other types of transistors.
In the conventional manufacturing method, there has been a problem as described below because of forming gate electrodes of the DDD transistor and the other types of transistors by the same polycrystalline silicon.
1. The number of manufacturing processes is great due to the necessity of the thermal diffusion process for sufficiently diffusing the DDD diffusion layer.
2. Since the thermal diffusion process is of a process conducted at a comparatively high temperature, there is deterioration in film properties of the insulating oxidized film, the gate. oxidized film and the like that has been formed prior to the thermal diffusion process.
3. There is difficulty in changing the gate oxidized film thickness for the DDD transistor and the other transistors. In order to carry out this requirement, there is a necessity for many more processes.
It is the purpose of the present invention to improve the conventional, structure and manufacturing method to eliminate, the above-stated problem.
SUMMARY OF THE INVENTION
In the structure and the manufacturing method of the present invention, after forming a gate of a DDD transistor and a lower electrode of a capacitance element by a first polycrystalline silicon, film and a DDD impurity layer is formed so that a DDD transistor is formed through a common thermal oxidation process and a DDD impurity diffusion process so as to form an insulating oxidized film for a capacitance element and a gate oxidized film for a transistor having a second polycrystalline silicon film as a gate electrode. Therefore the method has operational effects given as follows:
1. Manufacturing processes are reduced in number.
2. The reduction of heat treating processes improves the quality of the insulating oxidized film and the gate oxidized film.
3. Since the gate oxidation can be separately made between the DDD transistor and the other transistors, the thickness of, each of the gate oxidized films is easy to change.
REFERENCES:
patent: 4830974 (1989-05-01), Chang et al.
patent: 4833096 (1989-05-01), Huang et al.
patent: 5273923 (1993-12-01), Chang et al.
patent: 5286991 (1994-02-01), Hui et al.
patent: 5445987 (1995-08-01), Kuroda et al.
patent: 5801416 (1998-09-01), Choi et al.
patent: 5894147 (1999-04-01), Cacharrlis
Adams & Wilks
Chaudhuri Olik
Pham Hoai
Seiko Instruments Inc.
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