Method of producing co-planar Si and Ge composite substrate

Details Method of producing co-planar Si and Ge composite substrate Method of producing co-planar Si and Ge composite substrate

1999-01-04

2001-01-09

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Formation of semiconductive active region on any substrate

Fluid growth from gaseous state combined with preceding...

Reexamination Certificate

active

06171936

ABSTRACT:

BACKGROUND OF THE INVENTION
The invention relates to the field of lattice-mismatched semiconductor material integration, and in particular to the integration of SiGe materials onto a Si substrate.
As many lattice-matched devices and circuits mature, interest in lattice-mismatched semiconductors, devices, and circuits has increased. There are two driving forces behind the increased commercial interest: integration and component performance. Integrating dissimilar semiconductor materials on a common substrate allows the designer to improve performance, lower cost, and increase reliability. Thus, the most susceptible applications to this initial advance will be systems that require multiple types of semiconductor materials currently packaged separately and combined in a more conventional packaging solution. Examples of these applications are III-V materials integration on Si, and SiGe circuit integration with Si CMOS. Such single-chip systems are anticipated to have wide application in communication technologies, particularly wireless communications technologies.
The utility of combined dissimilar semiconductors relies on the quality of the resulting material. Large lattice-mismatch between the substrate and deposited layer creates stress during material deposition, creating many defects in the deposited layer, resulting in poor material quality and limited performance. To control threading dislocation densities in high mismatched deposited layers, there are only two well-established techniques: substrate patterning and composition grading. In the case of substrate patterning, the idea utilizes the knowledge that the threading dislocations are a necessity of geometry, i.e. that a dislocation cannot end in a crystal. If the free edge is brought closer to another free edge by patterning the substrate into smaller growth areas, then it is possible to reduce threading dislocation densities. This technique works best for low mismatched systems in which dislocation nucleation is not rampant; however, it will reduce threading dislocation densities in high mismatched systems as well.
The other well-established technique is the use of composition graded layers. One can imagine that to reach a large total mismatch, a series of low mismatched interfaces could achieve great relaxation but keep threading dislocation densities low. This result is possible if each layer becomes substantially relaxed and is able to reuse the threading dislocations from the layer below. This method was long ago applied in an empirical way to GaAsP LEDs grown on lattice-mismatched GaAs substrates. However, after the GaAsP process was transferred to manufacturing, most of the subsequent lattice-mismatch research focused on single mismatched interfaces. The driving force for lattice-mismatched materials in applications decreased as AlGaAs/GaAs structures and InGaAsP/InP structures dominated optoelectronic and electronic device applications. Until these materials systems were fully exploited, the implementation of high mismatched layers seemed unnecessary.
A renewed interest in graded layers has occurred due to the increased demand for novel components, as well as an increased demand for increased integration. The advances in relaxed graded SiGe have shown that SiGe devices based on relaxed SiGe on Si, and the integration of III-V materials on Si using intermediate relaxed SiGe graded layers are possible. Thus, relaxed, graded SiGe layers can act as the material bridge between SiGe devices and/or III-V devices and Si substrates.
These materials advances, however, are incomplete unless a proper process sequence can be found to create these relaxed layers and subsequent devices with relatively standard Si circuit processing. A critical view of electronic and optoelectronic systems shows that the main data processing in many applications can be executed in Si CMOS circuits, which dominate the semiconductor industry today. To create a new realm of Si-based single-chip systems, a structure and process to combine Si CMOS circuits with the materials advances in relaxed graded SiGe mentioned above, is necessary.
SUMMARY OF THE INVENTION
The invention provides a method of producing a co-planar SiGe/Si substrate. The SiGe regions are formed using relaxed graded SiGe technology. The planarization process described below creates a modified Si wafer which can proceed through the Si CMOS process. At a convenient point in the CMOS process, the devices on or in the SiGe regions can be metallized and connected to the CMOS circuit, creating a single-chip system utilizing Si devices, SiGe devices, and/or III-V devices.
The invention also provides a semiconductor structure and method for producing such a structure in which relaxed GeSi crystalline alloy surfaces can co-exist in a planar fashion with Si. Such a substrate is essential in harnessing the plethora of applications in which the integration of GeSi materials and devices, and/or III-V materials and devices grown on GeSi, with Si electronics is desired.
Accordingly, in accordance with one embodiment of the invention there is provided a semiconductor structure comprising a silicon wafer having silicon regions, and at least one Ge
x
Si
1−x
region integrated within the silicon regions. The silicon and Ge
x
Si
1−x
regions can be substantially coplanar surfaces. The structure can include at least one electronic device configured in the silicon regions, and at least one electronic device of III-V materials configured in the at least one Ge
x
Si
1−x
region. The structure can be, for example, an integrated III-V/Si semiconductor microchip.
In accordance with another embodiment of the invention there is provided a method of fabricating a semiconductor structure, comprising providing a silicon wafer with a surface; forming a pattern of vias within the surface of the wafer; and depositing regions of Ge
x
Si
1−x
within the vias. The method can include the step of processing the wafer so that the wafer and Ge
x
Si
1−x
regions have substantially coplanar surfaces. Another embodiment provides a method of fabricating a semiconductor structure, comprising providing a silicon wafer with a surface; depositing regions of Ge
x
Si
1−x
to the surface of the silicon wafer; and depositing silicon to the surface such that the deposited Ge
x
Si
1−x
regions are integrated within silicon.
These and other objects, features and advantages of the present invention will become apparent in light of the following detailed description of preferred embodiments thereof, as illustrated in the accompanying drawings.


REFERENCES:
patent: 3905037 (1975-09-01), Bean et al.
patent: 5243200 (1993-09-01), Kawasaki et al.
patent: 5256550 (1993-10-01), Laderman et al.
patent: 5602057 (1997-02-01), Kawasaki et al.
patent: 5648280 (1997-07-01), Kato
patent: 0 514 018 A2 (1992-04-01), None
Change, Y. et al., “Fabrication of Patterned GexSi1-x/Si Layers by Pulsed Laser Induced Exitaxy,” Applied Physics Letters, No. 19, (May 1991): 2150-2152.
Shichijo, H. et al., “Monolithic Process For Co-Integration of GAAS and Silicon Circuits,” International Electron Devices Metting, (Dec. 11, 1988): 778-781.

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