Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Utility Patent
1998-09-24
2001-01-02
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S335000
Utility Patent
active
06169309
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to semiconductor devices, and more specifically to power transistor circuits designed to withstand electrical transients.
BACKGROUND OF THE INVENTION
Output drive circuits for power applications require rugged high-breakdown voltage transistors that can withstand a harsh high-voltage, high-current environment. A common transistor for such applications is the lateral double-diffused metal-oxide-semiconductor transistor (LDMOS), which, despite its name, typically has a gate composed of highly-doped polycrystalline silicon rather than metal.
FIG. 1
shows a typical LDMOS transistor
100
. In operation, the source
102
and back gate
104
are typically coupled to electrical ground, and the drain
106
is coupled to a positive voltage supply. In the transistor's active state, a channel is formed in the p-type region
108
beneath the poly gate
110
by applying a positive voltage to the gate.
FIG. 2
is a schematic diagram of a prior art low-side LDMOS circuit. The breakdown of the zener diode stack DZ
1
forward biases the gate-source junction of the MOS transistor M
1
in the event of electrical transients on the drain terminal
200
. Such a transient may occur in an electrostatic discharge (ESD) event, for example, or as a result of inductive flyback from the drain bias network when the drain voltage supply is powered off. To protect the MOS transistor, the voltage drop of the zener stack plus the gate-to-source voltage drop should be less than the avalanche breakdown voltage of the MOS device. Certain transients may create a current between the gate and source terminals that may exceed the saturation current of the transistor. Such an over-current condition can result in catastrophic failure of the transistor. The current-voltage plot of
FIG. 3
illustrates the safe operating region A of the transistor and the region B in excess of the over-current limit. Because the protection approach shown in
FIG. 2
is ineffective in handling such over-current conditions, a more effective approach is needed.
SUMMARY OF THE INVENTION
In accordance with an embodiment of the invention, there is disclosed a circuit for protecting a transistor against electrical transients. The circuit comprises a first diode coupled between a power-supply-coupled first terminal and a control terminal of the protected transistor. The circuit also comprises a second diode and a resistor coupling the control terminal of the protected transistor to a reference potential. A second transistor is coupled in shunt to the protected transistor. The voltage on the control terminal of the second transistor is determined by the current through the resistor. The embodiments may be implemented in an integrated circuit wherein the second, shunting transistor is formed from parasitic elements within the semiconductor body in which the protected transistor is formed. In one embodiment, the protected MOS transistor is formed in an n-well and a shunting bipolar transistor is formed between the n-well and an n-doped guard ring formed adjacent to the n-well in the p-doped substrate.
One embodiment in accordance with the invention is a circuit including a first transistor. The first transistor includes a control terminal, a first terminal coupled to a power supply, and a second terminal coupled to a first reference potential. A first diode is coupled between the first terminal and the control terminal of the first transistor, while a second diode and a resistor are coupled between the control terminal of the first transistor and the first reference potential. The circuit also includes a second transistor, which includes a control terminal, a first terminal coupled to the power supply, and a second terminal coupled to a second reference potential. The control terminal of the second transistor is coupled between the second diode and the resistor.
Another embodiment is an integrated circuit including a semiconductor substrate doped a first conductivity type. A transistor is formed in a first doped region in the substrate, and the first doped region is doped a second conductivity type. A second doped region lies in the substrate adjacent and spaced apart from the first doped region, the second doped region being doped the second conductivity type. The integrated circuit also includes a base region, which is the region of the substrate between the first doped region and the second doped region. A base contact is made to the base region, and a contact is also made to the substrate elsewhere.
An advantage of the inventive concepts is that a circuit for protecting a transistor against voltage transients may be obtained from circuit elements, a guard-ring structure for example, conventionally available on an integrated circuit, but not heretofore utilized for this purpose. In addition, the concepts described do not rely on semiconductor-controlled rectifier (SCR) circuits, and thus avoid the risk of latching that those protective circuits present.
REFERENCES:
patent: 5159207 (1992-10-01), Pavlin et al.
patent: 5777362 (1998-07-01), Pearce
patent: 5825065 (1998-10-01), Corsi et al.
Baldwin David J.
Devore Joseph A.
Teggatz Ross E.
Brady W. James
Hoel Carlton H.
Meier Stephen D.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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