Method of producing an interconnect structure for an...

Details Method of producing an interconnect structure for an... Method of producing an interconnect structure for an...

2001-06-05

2003-04-15

Meier, Stephen D. (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S634000, C438S637000, C438S638000, C438S641000

Reexamination Certificate

active

06548396

ABSTRACT:

BACKGROUND OF THE DISCLOSURE
1. Field of the Invention
The invention relates to metallization and interconnect fabrication processes for fabricating integrated circuits and, more particularly, the invention relates to an improved dual damascene process for fabricating an interconnect structure within an integrated circuit.
2. Description of the Background Art
Damascene techniques have been developed in response to the stringent requirements on metal etch, dielectric gap fill and planarization that are used in modern integrated circuit fabrication. The main advantage of using a damascene technique is the elimination of metal etch and insulator gap fill steps within the process for fabricating interconnect structures. The elimination of metal etch steps becomes important as the industry moves from aluminum to copper metallization materials, since etching copper is difficult.
There are two kinds of damascene processes: single and dual. In a single damascene process for fabricating interconnect structures, as depicted in
FIGS. 1A-1G
, a first insulator
102
is deposited upon a substrate
100
and a via
104
is etched into the insulator
102
using, for example, a reactive ion etch (RIE) process. Then, the via
104
is filled with a metal layer
106
by metal deposition. The plug is planarized by, for example, chemical mechanical polishing (CMP) to form a “plug”
108
. Thereafter, a second insulator
110
is deposited atop the first insulator
102
and one or more trenches
112
are etched through the second insulator layer
110
using an RIE process. The trench
112
is then filled with a metal layer
114
using a metal deposition process to form an interconnection line that is then planarized by CMP. In this manner, a plurality of interconnect lines
116
are formed to conductively connect the plugs
108
to one another.
In a conventional dual damascene approach to forming interconnections, the vias and trenches are simultaneously filled with metal, thereby requiring fewer metallization and planarization steps in the fabrication process. Since both the line and via are simultaneously metallized in a dual damascene process, such structures eliminate any interface between the metal plug and the metal line.
More specifically, a dual damascene technique, as illustrated in
FIGS. 2A-2E
, deposits upon a substrate
200
an insulator
202
having a thickness that is equal to the via plus the trench depth. A mask
204
in the form of a via mask is deposited over the insulator
202
and one or more vias
206
are etched into the insulator. The mask is then removed, and a second mask
204
is formed, this being the trench mask. Thereafter, one or more trenches
210
are etched to a depth that approximately reaches the middle of the insulator
202
. As such, the trench depth is produced using a blind etch stop, i.e., the etch is stopped after a predefined period of time. Such a process is notoriously inaccurate for producing a repeatable and well-defined depth to the trench. Any undeveloped photoresist
212
from the second mask located within the via opening protects the via bottom from the etchant. The resist strip process used to remove the second mask has to be controlled to remove all of the resist from the via as well. Thereafter, both the trench
210
and the via
206
are metallized with a metal layer
214
in a single step and the structure is then planarized to form a trench and plug interconnect structure.
U.S. Pat. No. 5,635,423 discloses an improved dual damascene process. In this process, a first insulator is deposited to the desired thickness of a via. Thereafter, a thin etch stop layer is deposited over the first insulator layer and a second insulator having a thickness that is approximately equal to the desired trench depth is deposited on top of the etch stop layer. A photoresist mask (a via mask) is then formed atop the second insulator. Thereafter, an etch process is used to etch holes through the second insulator having a size equal to the via diameter. The etch is stopped on the etch stop layer. The via mask is then removed, and a trench mask is formed on top of the second insulator. Care must be taken that the resist is developed completely to the bottom of the via hole that was previously formed or the etch stop layer and first insulator will not be properly etched in subsequent process steps to form the via. Using the trench mask, trenches are etched in the second insulator and, simultaneously, the via is etched through the etch stop and the first insulator. Once the trench and via are formed, the structure can then be metallized to form the interconnects.
In this process, if any photoresist remains in the via in the second insulator, then the via will not be formed, or improperly formed, in the first insulator layer. Also, if the trench edge is crossing the via, a partial amount of photoresist will be left in the via, then the via will not be formed completely and will be distorted. Such an incomplete via will generally result in an interconnection failure.
Therefore, a need exists in the art for a dual damascene process that forms an interconnect structure without the detrimental need for complete removal of the photoresist used to define the via, even when the trench edge is crossing the via.
SUMMARY OF THE INVENTION
The disadvantages associated with the prior art techniques used for forming metal interconnections are overcome by the present invention of a dual damascene technique that forms a complete via in a single step. Specifically, the method of the present invention deposits a first insulator layer upon a substrate, an etch stop layer over the first insulator layer, and a second insulator layer atop the etch stop layer. A via mask is then formed, for example, by a spin-on chemical vapor deposition or (CVD) photoresist which is developed and patterned according to the locations of the dimensions of the ultimate via or vias. Thereafter, the first insulator layer, the etch stop layer and the second insulator layer are etched in a single step, for example, using a reactive ion etch process. The hole that is formed through these three layers has the diameter of the ultimate via. Thereafter, a photoresist strip process is performed to remove all of the photoresist used to form the via mask. A second mask, the trench mask, is then formed, for example, by spinning on a photoresist, developing and patterning that photoresist. The pattern defines the location and dimensions of the trench or trenches to be formed in the second insulator layer. During the developing of the trench mask, the resist may not be developed completely from the via, i.e., some photoresist purposefully remains within the via. Thereafter, the trench is etched into the second insulator layer using reactive ion etch process. The undeveloped photoresist that may remain in the via after the trench mask is formed protects the via during the trench etch process from becoming etched even further. The stop layer creates a wide process window within which to etch the trench. As such, using the process of the present invention, it is not important that the trench edge might cross the via and that photoresist is left in a via, since the via is completely formed before the trench lithography. Once the trench is formed, the trench mask is removed and both the trench and via are metallized simultaneously. Thereafter, the metallization is planarized by chemical mechanical polishing (CMP) or an etch-back process.
To continue the interconnect structure toward creating a multi-level structure, a passivation layer is deposited atop the structure formed above. Then the process is repeated to fabricate another dual damascene structure. Prior to metallization of the upper structure, the passivation layer is etched to open a contact via to the underlying structure. The upper structure is then metallized and planarized to form a second level of the multi-level interconnect structure. The process can be repeated again and again to add additional levels.
The process for creating a dual damascene interconnect structu

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