Method of producing an EPROM with a trench insulating layer

Details Method of producing an EPROM with a trench insulating layer Method of producing an EPROM with a trench insulating layer

1996-01-29

1998-03-24

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438296, 438426, H01L 218247

Patent

active

057312370

ABSTRACT:
An EPROM allowing a miniaturization of an isolation region (a field insulating layer) without generating a parasitic transistor. The EPROM comprises a semiconductor substrate; a field insulating layer defining a device formation region of the semiconductor substrate; a gate insulating layer; a floating gate formed on the field insulating layer and the field insulating layer; a trench insulating layer extending into the semiconductor substrate at the center portion of the field insulating layer, one of the side walls of the trench insulating layer being self-aligned with the end face of the floating gate; a first interlaminar insulating layer covering the floating gate; a control gate located above the floating gate; a second interlaminar insulating layer formed over the whole surface; and a bit line.

REFERENCES:
patent: 4326331 (1982-04-01), Guterman
patent: 4679304 (1987-07-01), Bois
patent: 4713677 (1987-12-01), Tigelaar et al.
patent: 4835115 (1989-05-01), Eklund
patent: 5045489 (1991-09-01), Gill et al.
patent: 5051795 (1991-09-01), Gill et al.
patent: 5111257 (1992-05-01), Andoh et al.
patent: 5451803 (1995-09-01), Oji et al.

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