Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-01-11
2003-10-21
Meier, Stephen D. (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S401000, C438S462000, C438S631000
Reexamination Certificate
active
06635567
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a method for producing alignment marks in a structure with integrated circuits.
Such structures with integrated circuits may be formed, in particular, by DRAM cell configurations incorporated in a semiconductor substrate formed by a wafer.
In particular for the wiring of the integrated circuits, a plurality of layers lying one above the other are applied to the semiconductor substrate, systems of interconnects made of metal running in the layers. For this purpose, an insulator layer, which is formed, in particular, by an oxide layer, is applied to the semiconductor substrate in particular directly or with the interposition of further layers. In order to fabricate the connections of interconnects, contact holes are etched into said insulator layer. The contact holes thus fabricated are then filled with metal, preferably tungsten. By means of a CMP (chemical mechanical polishing) process, the surface of the oxide layer, in particular metal projecting above the upper edges of the contact holes, is then polished in a planar fashion. A metal layer is subsequently applied to the oxide layer. For the patterning of this metal layer, a resist mask is subsequently applied.
One problem here is the necessity of exactly aligning the resist mask on the metal layer. In particular, the resist mask has to be aligned with the structure of the interconnects in the oxide layer. However, since the metal layer is opaque, the structures in the oxide layer cannot directly be detected optically. Therefore, the alignment marks are arranged in the metal layer as local depressions which can be detected by optical measuring instruments such as laser interferometers for example.
In order to fabricate such alignment marks, alignment trenches are etched into the oxide layer at predetermined locations. These alignment trenches are etched together with the contact holes into the oxide layer. Afterwards, the contact holes as well as the alignment trenches are filled with metal, whereupon the surface processing by means of the CMP process takes place.
The widths of the alignment trenches are considerably greater than the widths of the contact holes. Typically, the width of a contact hole is about 0.3 &mgr;m, while the width of an alignment trench is about 2 &mgr;m.
The consequence of this is that, as a result of the pressure on the top sides of the metal layers during the polishing operation of the CMP process, the metal surfaces of the metal layers in the alignment trenches are lowered, but the metal surfaces of the metal layers in the contact holes are not. This is due to the fact that the metal layer, in particular when tungsten is used, is softer than the oxide layer. With the small widths of the contact holes, during the polishing operation the oxide layer exercises a supporting effect which extends over the entire area of a contact hole. Since the widths of the alignment trenches are considerably greater than the widths of the contact holes, the supporting effect of the oxide layer acts only in the edge regions of the alignment trenches, resulting in each case in a lowering of the metal surface in the center of the alignment trenches during the CMP process.
These lowered portions form profiles for the alignment marks, the alignment marks lying above the alignment trenches after the deposition of the metal layer. In this case, the alignment marks are designed as depressions which essentially correspond to the profiles produced beforehand.
In order that the alignment marks can be detected by the respective optical measuring instruments, the transitions between the planar metal surface and the depressions forming the alignment marks must fall as steeply as possible in the edge regions. Furthermore, the alignment marks must be able to be fabricated reproducibly in order that they can be reliably detected by the measuring instruments. It has been shown that these requirements can be fulfilled only inadequately in the case of conventional prior art alignment marks of this type.
An essential problem in the fabrication of alignment marks of this type is that the lowering of the metal surface in the CMP process cannot be fabricated reproducibly. Accordingly, the profiles of the depressions forming the alignment marks vary for different production batches, as a result of which they become more difficult to measure or their measurement is corrupted. A further problem is that during the CMP process, residues of polishing agent settle in the lowered portions of the metal layers of the alignment trenches. On account of the lack of reproducibility in the formation of the lowered portions, the surfaces of the latter have irregularities in which the residues of polishing agent collect in such a way that they can no longer be removed. In this case, the residues of polishing agent collect, in particular, in the edge regions of the lowered portions. This in turn has the effect that the profiles of the lowered portions no longer have the necessary steepness in the edge regions, so that, accordingly, only gently falling edges with shallow slopes are obtained in the case of the alignment marks. As a result, the alignment marks can no longer be detected sufficiently reliably by the measuring instruments.
U.S. Pat. No. 5,869,383 describes a method for producing alignment marks which are used for aligning a laser on a semiconductor substrate. The semiconductor substrate comprises a silicon wafer and has a configuration of integrated circuits forming a DRAM cell arrangement, for example. To ensure that defective circuits arising during the fabrication of such DRAM cell arrangements do not lead to defective functioning of the entire DRAM cell arrangement, at least some of the circuits are designed to be redundant. If one of the doubly provided circuits is defective, then it is deactivated and the assigned corresponding circuit is activated.
Specific circuits are deactivated by means of the laser by a fusible layer segment which is applied on the semiconductor substrate being melted. This layer segment is preferably composed of polysilicon. This polysilicon layer segment is applied to the semiconductor substrate with the interposition of an insulator layer. A plurality of dielectric intermediate layers are applied to the polysilicon layer segments and the semiconductor substrate.
A passivation layer made of silicon oxide or silicon nitride is applied to these dielectric intermediate layers. The passivation layer has a layer thickness in the range between 200 nm and 1000 nm.
A resist layer is applied to this passivation layer for the purpose of forming a resist mask. By means of a photolithographic process, a hole pattern is produced in the resist layer. By means of an etching process, preferably an RIE (reactive ion etching) method, recesses are produced in the dielectric intermediate layers through the holes in the resist mask. These recesses lie above the polysilicon layer segments, the depths of the recesses being chosen such that the bottom of a recess in each case lies closely above the respective polysilicon layer segment. In order to deactivate integrated circuits, the laser beams emitted by the laser are then guided into the respective recesses, the underlying polysilicon layer segments thereby being melted.
The laser is aligned by means of the alignment marks. In order to fabricate the alignment marks, a metal layer is applied to the surface of the topmost dielectric intermediate layer at predetermined locations. An antireflection layer is then applied to this metal layer. The passivation layer is subsequently applied to the entire substrate, which layer covers the uncovered parts of the uppermost dielectric intermediate layer and also the metal layer with the antireflection layer lying on it.
The resist layer is then applied to the antireflection layer. During the photolithographic process for producing the hole pattern, a hole pattern is produced in the resist layer and is used, in the subsequent etching process, to produce not only the recesses in
Ebertseder Eva
Hanebeck Jochen
Lehr Matthias
Pahlitzsch Jürgen
Werneke Torsten
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
Meier Stephen D.
Perkins Pamela
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