Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-01-18
2002-01-08
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S158000, C257S302000, C326S119000
Reexamination Certificate
active
06337247
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention lies in the integrated technology field. More specifically, the invention relates to a vertical MOS transistor with a particularly small channel length and good radiofrequency and logic properties.
With a view to ever-faster components with higher integration density, the structure sizes of integrated circuits are decreasing from generation to generation. This holds equally true in the context of CMOS technology. It is generally expected (see, for example, Roadmap of Semiconductor Technology, Solid State Technology 3, (February 1995)) that MOS transistors with a gate length of less than 100 nm will be used by the year 2010.
Attempts have been made, on the one hand, to scale customary modern CMOS technology in order to develop planar MOS transistors with such gate lengths (see, for example, A. Hori, et al., “A 0.05 &mgr;m-CMOS with Ultra Shallow Source/Drain Junctions Fabricated by 5 keV Ion Implantation and Rapid Thermal Annealing,” IEDM 1994, 485; and H. Hu, et al., “Channel and Source/Drain Engineering in High-Performance Sub-0.1 &mgr;m NMOSFETs Using X-Ray Lithography,” Symposium on VLSI Technology, 17, 1994)). The production of such planar MOS transistors with channel lengths of less than 100 nm requires the use of electron beam lithography and has hitherto been possible only on a laboratory scale. The use of the electron beam lithography leads to a more than proportional increase in production costs.
In parallel with those efforts, vertical transistors are being investigated. Since the channel length extends vertically in relation to a surface of a substrate, the surface area of a vertical transistor can be smaller than that of conventional planar transistors. A further reduction in area is obtained by reducing the channel width required for a given current, by shortening the channel length. Risch et al., in “Vertical MOS Transistor with 70 nm Channel Length,” ESSDERC 1995, pages 101-04, describe vertical MOS transistors with short channel lengths. In order to produce those vertical MOS transistors, layer sequences are formed corresponding to the source, channel and drain, and are annularly surrounded by the gate dielectric and gate electrode. The channel lengths of vertical MOS transistors are small compared with those of conventional planar transistors. In terms of their radiofrequency and logic properties, vertical MOS transistors have to date been unsatisfactory in comparison with planar MOS transistors. This is attributable, on the one hand, to parasitic capacitances of the overlapping gate electrode and, on the other hand, to the formation of a parasitic bipolar transistor in the vertical layer sequence.
H. Takato et al. IEDM 88, pages 222-25 describes a vertical MOS transistor whose gate electrode annularly surrounds a cuboid layer structure in which a first source/drain region and a channel layer are arranged. The annular arrangement of the gate electrode increases the space-charge zone, which leads to a reduction in the stray capacitance. The channel length of the MOS transistor is large and corresponds to that of conventional planar transistors. The layer structure is produced using a lithographic method, and preferably has a lateral width of about 1 &mgr;m, so that the space-charge zone fills the entire channel layer. The radiofrequency and logic properties of the vertical MOS transistor are therefore comparable with those of planar MOS transistors.
SUMMARY OF THE INVENTION
The object of the invention is to provide a method of producing a vertical MOS transistor which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this kind, and in which the radiofrequency and logic properties of the vertical MOS transistor are made comparable with those of planar MOS transistors, and the channel length of the vertical MOS transistor is made particularly small.
With the above and other objects in view there is provided, in accordance with the invention, a method of producing a vertical MOS transistor, which comprises:
providing a substrate of semiconductor material having a surface defining an axis extending perpendicularly to the surface;
forming a layer structure on the substrate with an etching process in which a spacer is used as a mask;
the layer structure having mutually opposite flanks extending parallel to the axis and including at least one first source/drain region and a channel layer below the first source/drain region relative to the axis;
forming a gate dielectric and a gate electrode at least in an area of the channel layer on the mutually opposite flanks of the layer structure; and
forming a second source/drain region below the channel layer relative to the axis.
In other words, the vertical MOS transistor is formed with a first source/drain region and a channel layer as parts of a layer structure. At least in the area of the channel layer, the layer structure is provided on at least two sides, i.e. at least on two opposite flanks of the layer structure, with a gate dielectric and a gate electrode. A first part of the gate electrode, which is next to a first of the two opposite flanks, and a second part of the gate electrode, which is next to a second of the two opposite flanks, are connected to one another, e.g. via a contact or a web. The gate electrode may also be formed continuously. In contrast to a one-sided arrangement, with the two-sided arrangement the channel width is doubled, without the surface area of the vertical MOS transistor therefore being increased, and the current is thereby increased and the formation of space-charge zones between the two flanks in the channel layer is enhanced. This is advantageous since, in space-charge zones, no leakage currents are created owing to a parasitic bipolar transistor.
Space-charge zones become commensurately larger as the dopant concentration in the channel layer is reduced. However, since the intention is to produce a short channel length, the channel layer must be heavily doped in order to avoid leakage currents due to punch-through. In order to obtain a space-charge zone throughout the channel layer, a dimension between the two opposite flanks of the layer structure must accordingly be particularly small. To that end, the layer structure is produced with the aid of a spacer acting as a mask. The dimension between the two opposite flanks of the layer structure becomes so small that, when the gate electrode is driven appropriately, the vertical MOS transistor becomes fully depleted. With a conventional voltage of from 0V-2V, the dimension is about 30 nm to 90 nm.
A second source/drain region may be arranged as part of the layer structure under the channel layer. It is advantageous if the second source/drain region is not part of the layer structure, but is produced essentially laterally with respect to the layer structure. As a result of this, on the one hand, the heavily doped first source/drain region and the heavily doped second source/drain region can be produced in self-aligned fashion by implantation, i.e. without using masks to be aligned. The first source/drain region is in this case arranged over the channel layer. On the other hand, the channel layer can be connected to a substrate of semiconductor material, which prevents floating-body effects in the channel layer should the latter not be fully depleted. In this case, the substrate is doped with the conductivity type of the channel layer in a layer next to the channel layer. The conductivity type of the layer may, however, also be chosen independently of the conductivity type of the channel layer. The conductivity type of the first source/drain region and of the second source/drain region can be swapped with the conductivity type of the channel layer.
The second source-drain region may also be formed as part of the layer structure, and/or adjoin the channel layer from below.
It is within the scope of the invention to produce the layer structure by structuring a layer sequence. For the layer sequence, at least one first layer doped wit
Äugle Thomas
Risch Lothar
Rösner Wolfgang
Schulz Thomas
Greenberg Laurence A.
Infineon - Technologies AG
Lerner Herbert L.
Smith Matthew
Stemer Werner H.
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