Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-03-10
2001-07-17
Fourson, George (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S373000, C257S375000
Reexamination Certificate
active
06262457
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a method for producing a transistor structure, in particular a MOS transistor structure, and to a transistor structure.
In many applications of modern electronics, the problem arises that, besides the pure processing of information, the electronic product must also interact with its environment in some way. One example of this involves the control system for an airbag, which on the one hand evaluates the signals measured by an acceleration sensor and on the other hand triggers the airbag in the event of an accident.
For economic reasons, it would be advantageous if all these different functions could be integrated in a single semiconductor product. However, the production of such “smart-power” products places great demands on the production process which is used. Thus, for example, a variety of component types, such as CMOS transistors, DMOS power transistors and bipolar transistors, need to be integrated with high packing density on a chip. However, the production process should at the same time involve a minimum number of dopant implantation and dopant diffusion steps, and few masking planes.
The number of dopant implantation and dopant diffusion steps is customarily reduced by using one dopant implantation and dopant diffusion step, as well as the resulting dopant profile, for a plurality of different components. In this case, however, it must be taken into account that different components have different requirements in terms of their doping profile. For example NMOS and DMOS transistors require a specific surface concentration of the dopant in the region of the p-channel in order to give a defined transistor threshold voltage. In the case of JFETs and controllable resistors, it is advantageous to provide a weakly doped flat P-area. However, in order to improve the invulnerability of an NMOS transistor to latch-up, it is necessary to form a p-well with a low film resistance. A deep rectangular profile would be ideal for this purpose.
Since these different requirements cannot be covered by one doping profile, but on cost grounds it is only possible to have a few dopant implantation and dopant diffusion steps, it has not to date been possible to set optimum doping profiles for the respective component. In particular, it has not been possible to produce a p-well with a deep rectangular profile, as would be beneficial for NMOS transistors, since this would result in a very high degree of lateral diffusion out of the p-wells, in particular the p-wells of other components.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method of producing a transistor structure and a transistor structure, particularly a MOS structure, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which makes it possible to have doping profiles matched to the transistor structure without additional masking planes or additional implantation steps. The primary object with regard to the product is to provide a transistor structure with matched doping profile.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method of producing a transistor, specifically a MOS transistor, with comprises the following steps:
introducing a dopant of a first conductivity type into a semiconductor substrate;
introducing a dopant of a second conductivity type into the semiconductor substrate;
forming an epitaxial layer on the semiconductor substrate;
introducing a further dopant of the second conductivity type into the epitaxial layer; heat treating the semiconductor substrate and the epitaxial layer and causing the dopant of the second conductivity type in the semiconductor substrate and the dopant of the second conductivity type in the epitaxial layer to diffuse out and to form a coherent semiconductor region, and causing the dopant of the first conductivity type in the semiconductor substrate to diffuse out and to form a buried zone;
forming at least a first insulator layer on the semiconductor region of the second conductivity type and structuring the first insulator layer;
forming at least one conducting layer on the first insulator layer and structuring the conducting layer; and
introducing a further dopant of the first conductivity type into the semiconductor region of the second conductivity type, and driving in the further dopant to form zones of the first conductivity type in the semiconductor region of the second conductivity type.
With the above and other objects in view there is also provided, in accordance with the invention, a transistor structure, comprising:
a semiconductor substrate;
an epitaxial layer formed on the substrate;
a buried zone of a first conductivity type disposed at an interface boundary between the semiconductor substrate and the
epitaxial layer in the semiconductor substrate and in the epitaxial layer;
a semiconductor region of a second conductivity type disposed in the epitaxial layer in contact with the buried zone;
zones of the first conductivity type formed at the surface of the semiconductor region;
at least a first insulator layer disposed on the surface of the semiconductor region between the zones; and
at least one conducting layer formed on the first insulator layer.
The primary advantage of the invention is that it provides for additional degrees of freedom for optimizing the component properties by combining two doping profiles. The threshold voltage of the NMOS or DMOS transistors can be set through the process parameters involved in the introduction and outward diffusion of the further dopant of the second conductivity type, independently of the deep concentration, since the dopant concentration at the surface can be chosen independently of the dopant concentration at depth. The low sheet resistance results from the large penetration depth of the semiconductor region through the combination of the two dopant profiles. The low film resistance leads to reduced pinching of the substrate current in an NMOS transistor, and to greater stability against “latch-up”, without substantially increasing the concentration of the dopants in the region of source/drain diffusions, and therefore without unfavorably affecting drain/bulk capacitance. In addition, the concentration of the further dopant of the second conductivity type can be kept low, by means of which a semiconductor region of a second conductivity type is achieved which exhibits little outward lateral diffusion. Further, when the components are given the conventional polarity, the semiconductor region is insulated from the p-substrate by the buried zone.
In accordance with an added feature of the invention, oxide regions are produced at the edge of the semiconductor region which ensure that the transistor structure is insulated. It is in this case particularly preferable for the oxide regions to be produced by a LOCOS process.
In accordance with an additional feature of the invention, at least one deep diffusion area is produced in contact with the buried zone. It is in this case particularly preferable for the deep diffusion area to be produced by a furnace process and a heat treatment.
In accordance with a concomitant feature of the invention, at least one insulation area is produced. The insulation area is preferably produced by a dopant of the second conductivity type, which has been introduced into the semiconductor substrate, and a dopant of the second conductivity type, which has been introduced into the epitaxial layer, diffusing out and forming the insulation area.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for producing a transistor structure, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the s
Gutheit Tim
Schwetlick Werner
Stecher Matthias
Fourson George
Greenberg Laurence A.
Infineon - Technologies AG
Lerner Herbert L.
Stemer Werner H.
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