Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1998-07-16
2001-07-24
Verbrugge, Kevin (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
Reexamination Certificate
active
06266738
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory controlling method and a memory controlling apparatus having communication capabilities required in transferring data between a memory including a DRAM (dynamic random access memory) divided into a plurality of blocks and a device having the capability of inputting and outputting data.
2. Description of the Related Art
According to a common technique, a DRAM is generally controlled in such a manner that read/write cycles and and refresh cycles are assigned to respective blocks of the memory so that when a read/write cycle is performed in a certain block, a refresh cycle is performed in another block, thereby ensuring that data can be transferred while maintaining the memory contents in the DRAM.
It is also known in the art to introduce competition between read/write and refresh cycles so that when a cycle is completed another cycle is started in accordance with predetermined priority, thereby ensuring that data transfer is performed without losing the contents of the DRAM.
However, in the former conventional technique, control signals are simultaneously applied to the respective blocks, and thus a large current is consumed when the control signals are simultaneously applied. That is, extremely great peaks appear in the current. Such large currents cause instantaneous variations in the power supply voltage, or result in noise. As a result, a reduction in the reliability of the apparatus occurs.
Although the latter conventional technique does not have such a problem, it has another problem that, in order to ensure that the contents of the memory are maintained without being lost, the ratio of the refresh cycles to the read/write cycles is often set to a value rather greater than required. This results in a reduction in the data transfer rate.
SUMMARY OF THE INVENTION
In view of the above, it is an object of the present invention to provide a method and apparatus for controlling a memory in such a manner that data is transferred at a high rate without performing a greater number of refreshing operations than required.
It is another object of the present invention to provide a method and apparatus for controlling a memory in such a manner that when a data transfer cycle is performed according to the ratio determined so that a shorter period is assigned for performance of refresh cycles than to that for data transfer cycles, if a period of time longer than allowed has elapsed, then a refreshing operation is performed, out of turn thereby preventing the contents of the memory from being lost.
According to an aspect of the present invention, there is provided a memory controlling apparatus having the capability of performing communication between a memory including a DRAM divided into a plurality of blocks and a device capable of inputting and outputting data, the apparatus comprising:
first control means for transferring data between the memory and the device and also refreshing the memory while adjusting the frequencies of data transferring operations and refreshing operations; and second control means for controlling the timing in terms of the data transferring and refreshing operations, depending on the status of the communication between the memory and the device and also depending on designated values of the frequencies of data transferring and refreshing operations.
REFERENCES:
patent: 5418920 (1995-05-01), Kuddes
patent: 5638529 (1997-06-01), Yee
patent: 5742834 (1998-04-01), Kobayashi
patent: 5761703 (1998-06-01), Bolyn
patent: 5822753 (1998-10-01), Takano
patent: 5890198 (1999-03-01), Pawlowski
patent: 5991851 (1999-11-01), Alwais et al.
Canon Kabushiki Kaisha
Fitzpatrick ,Cella, Harper & Scinto
Verbrugge Kevin
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