Method of producing a stacked capacitor

Details Method of producing a stacked capacitor Method of producing a stacked capacitor

1999-07-16

2001-02-20

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S253000, C438S398000, C438S397000, C257S306000

Reexamination Certificate

active

06190964

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The present invention pertains to a fabrication method for producing a stacked capacitor.
Although applicable to any desired stacked capacitors, the present invention and also the problems on which it is based will be described and explained herein with regard to a stacked capacitor for use in a semiconductor memory device, for instance a DRAM (dynamic read/write random access memory).
Integrated circuits (ICs) or chips use capacitors for the purpose of storing charge. One example of an IC which uses capacitors for storing charges is a memory IC, such as for instance a chip for a dynamic random access memory (DRAM). The charge state (“0” or “1”) in the capacitor thereby represents a data bit.
A DRAM chip contains a matrix of memory cells connected up in the form of rows and columns. The row connections are usually designated as word lines and the column connections as bit lines. Data are read from the memory cells or data are written to the memory cells by the activation of suitable word lines and bit lines.
A DRAM memory cell usually contains a selection transistor connected to a capacitor. The transistor contains two diffusion regions separated by a channel, above which a gate is disposed. Depending on the direction in which the current flows, one diffusion region is designated as the drain and the other as the source. The designations “drain” and “source” are in this case used mutually interchangeably with regard to the diffusion regions. The gates are connected to a word line, and one of the diffusion regions is connected to a bit line. The other diffusion region is connected to the capacitor. The application of a suitable voltage to the gate switches the selection transistor on, enables current to flow between the diffusion regions through the channel in order, in this way, to form a connection between the capacitor and the bit line. The switch-off of the selection transistor disconnects this connection by interrupting the flow of current through the channel.
The charge stored in the capacitor decreases with time on account of an inherent leakage current. Before the charge has decreased to an undetermined level (below a threshold value), the storage capacitor must be refreshed.
The continual striving to reduce the size of memory devices demands that DRAMs be designed with a greater density and a smaller characteristic size, that is to say a smaller memory cell area. In order to fabricate memory cells that occupy a smaller surface region, components having a smaller base area are required.
A reduction in the base area of a capacitor generally leads to a smaller capacitance, which has to be compensated for by the construction of the capacitor. This is because an excessively small capacitance of the storage capacitor can adversely affect the functionality and usability of the memory device. In particular, the amplitude of the output signal and the refresh rate of a memory cell depend on the magnitude of the capacitance.
With reference to
FIG. 3
, there is shown a schematic of the equivalent circuit diagram for a stacked capacitor for use in a semiconductor memory device. The designation BL thereby refers to a bit line, WL to a word line, AT to a selection transistor and D, S, G to drain, source, gate, respectively, of the selection transistor AT. The designation K refers to the capacitor per se.
There are three kinds of integrated capacitors: planar capacitors, trench capacitors, and stacked capacitors. Planar capacitors are the general standard; trench and stacked capacitors are used particularly in megabit DRAMs because trench capacitors and stacked capacitors have a larger capacitance than planar capacitors given the same base area.
A higher capacitance is achieved by the trench capacitor and stacked capacitor having a three-dimensional structure whose surface area is significantly greater than its base area. The fabrication of this three-dimensional structure generally requires an additional fabrication outlay.
The trench capacitor makes use of the fact that the wall area of a trench etched deeply into the base material is much larger than its base area.
In particular, a distinction is made between trench capacitors with a polysilicon plate and trench capacitors with a buried plate.
A stacked capacitor comprises, in principle, a plurality of planar capacitors which are arranged one above the other and whose electrodes are connected in parallel. Examples of known stack capacitors are a crown stacked capacitor and a rough silicon stacked capacitor.
Further details on trench and stacked capacitors may be found for example in Widmann, Mader, Friedrich: “Technologie hochintegrierter Schaltungen” [Technology of Large Scale Integrated Circuits], 2d ed., Berlin, 1996, pages 273, 292f.
In these customary trench and stack designs, a reduction of the capacitor base area can generally be achieved only by means of a higher lateral resolution in the photolithography. The depth of the trenches or the edge length of the stacks is limited by the trench etching technology.
With reference to
FIG. 4
, there is shown a diagrammatic view of a prior art stacked capacitor for use in a semiconductor memory device.
In
FIG. 4
, P
1
-P
4
designates polysilicon layers,
10
designates a silicon semiconductor substrate,
20
designates an n
+
-type well,
150
designates gate structures,
400
designates an oxide layer and
450
designates ONO layers (ONO=oxide
itride/oxide).
FIG. 4
shows the so-called fin cell which is used in particular in a 16-MB DRAM application. As many polysilicon layers P
1
-P
4
as desired can be stacked one on top of the other. The fabrication of such a capacitor with 2n layers requires 2n−1 photoplanes and process control with n−1 sacrificial layers. The process control is therefore quite complicated.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a stacked capacitor and a corresponding production process, which overcome the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which enables the integration of large capacitances on a small silicon base area in a simple manner without a high outlay in terms of process engineering.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method of fabricating a stacked capacitor, which comprises the following steps:
providing a semiconductor substrate of a first conductivity type and a well of a second conductivity type formed in the substrate;
forming a stack of alternating first conductive layers of the first conductivity type and second conductive layers of the second conductivity type, with respective insulation layers interposed therebetween, on the semiconductor substrate;
selectively etching the second conductive layers at a first edge region of the stack and undercutting the second conductive layers with respect to the first conductive layers to form undercuts;
forming insulation bridges at the undercuts to provide continuous insulation of the second conductive layers towards the first edge region;
forming a first spacer of a conductive material at the first edge region of the stack, and connecting the first spacer to the semiconductor substrate and to the first conductive layers; and
forming a second spacer of a conductive material at a second edge region of the stack, and connecting the second spacer to the well and to the second conductive layers.
In accordance with an added feature of the invention, the method includes the following further steps which are performed prior to the step of forming the spacer:
selectively etching the second conductive layers at the second edge region of the stack, to undercut the second conductive layers with respect to the first conductive layers and forming undercuts;
forming an etching stop layer at the undercuts;
etching the first conductive layers at the second edge region of the stack, to undercut with respect to the second conductive layers and forming second undercut

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