Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-06-10
2001-01-30
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S267000, C438S268000, C438S589000
Reexamination Certificate
active
06180458
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention pertains to memory cells and to the production of such memory cells.
In order to store large volumes of data, for example in data processing (DP) applications or for the digital storage of music or images, use is mainly made at present of memory systems which have mechanically moving parts such as, for example, hard disk storage, floppy disks or compact discs. The moved parts are subject to mechanical wear. Furthermore, they require a comparatively large volume and permit only slow data access. Moreover, since they are sensitive with regard to vibrations and positioning, and they have a comparatively high power consumption for their operation, these memory systems can be used in mobile systems only to a limited extent.
Relatively small volumes of data are usually in semiconductor-based read-only memories (ROM). These are often realized as planar, integrated silicon circuits in which MOS transistors are used as memory cells. The transistors are selected via the gate electrode which is connected to the word line. The input of the MOS transistor is connected to a reference line and the output is connected to a bit line. An assessment is made during the read operation, as to whether or not a current is flowing through the transistor. Logic values zero and one are assigned correspondingly. The storage of zero and one is effected in technical terms in that no MOS transistor is produced or no conductive connection to the bit line is realized in memory cells in which the logic value assigned to the state “no current flow through the transistor” is stored. As an alternative, MOS transistors which have different threshold voltages due to different implantation in the channel region can be realized for the two logic values.
The semiconductor-based memories permit random access to the stored information. The electrical power required to read the information is distinctly less than in the case of the above-mentioned memory systems which have mechanically moved parts. Since no moved parts are required, concerns with regard to mechanical wear and sensitivity to vibrations do not apply here. Semiconductor-based memories can therefore be used for mobile systems as well.
The above-mentioned silicon memories have a planar structure. A minimum area requirement thus becomes necessary for each memory cell and is 4 F
2
in the most favorable case, where F is the smallest structure size that can be produced with the respective technology.
The use of vertical MOS transistors in a read-only memory is disclosed in U.S. Pat. No. 4,954,854 to Dhong et al. The surface of a silicon substrate is provided with trenches, in that system, which are adjoined at the bottom by a source region, which are adjoined at the surface of the substrate by a drain region, and along whose sides a channel region is arranged. The surface of the trench is provided with a gate dielectric and the trench is filled with a gate electrode. Zero and one are differentiated in that configuration in that no trench is etched and no transistor is produced for one of the logic values.
A read-only memory cell configuration whose memory cells comprise MOS transistors is disclosed in German patent publication DE 42 14 923 A1. There, MOS transistors are arranged along trenches in such a way that a source region adjoins the bottom of the trench, a drain region adjoins the surface of the substrate, and a channel region adjoins at the side and bottom of the trench both vertically with respect to the surface of the substrate and parallel to the surface of the substrate. The surface of the channel region is provided with a gate dielectric. The gate electrode is designed as a spacer (edge cover). The logic values zero and one are differentiated by different threshold voltages, which are effected by channel implantation. During the channel implantation, the implanting ions impinge on the surface of the respective trench at such angles that implantation is deliberately effected only along one side due to shading effects of the opposite side.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a memory cell configuration and a method for producing same, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which provides for a semiconductor-based memory cell configuration with increased storage density, which is suitable as a read-only memory for large volumes of data, and which can be produced with few production steps and at a high yield.
With the foregoing and other objects in view there is provided, in accordance with the invention, a memory cell configuration, comprising:
a semiconductor substrate having a main area and a multiplicity of memory cells disposed on said main area of said semiconductor substrate, each of the memory cells comprising at least one MOS transistor;
said memory cells including first memory cells formed as planar MOS transistors disposed in mutually parallel rows;
the semiconductor substrate having strip-like trenches with walls and a trench bottom formed therein which extend parallel to the mutually parallel rows;
the mutually parallel rows being disposed alternately on the trench bottom of the trenches and on the main area between mutually adjacent trenches; and
the memory cells including second memory cells formed as MOS transistors, the MOS transistors of the second memory cells being vertical with respect to the main area and being formed on the side walls of the trenches.
In accordance with the invention there is also provided a method of producing a memory cell configuration. The method comprises the following steps:
etching a plurality of substantially parallel, strip-like trenches with a trench bottom and side walls into a main area of a semiconductor substrate;
forming planar MOS transistors on said trench bottoms and on the main area between adjacent trenches; and
forming vertical MOS transistors on the side walls of the trenches.
The memory cell configuration according to the invention is realized in a semiconductor substrate. A semiconductor substrate is preferably used which has monocrystalline silicon at least in the main area. Both a monocrystalline silicon wafer and an SOI substrate are suitable as the semiconductor substrate.
The memory cell configuration has a multiplicity of memory cells which each comprise at least one MOS transistor. In this case, first memory cells comprise planar MOS transistors arranged in rows which run in parallel. Strip-like trenches which essentially run in parallel and run parallel to the rows are provided in the main area of the semiconductor substrate. The rows are arranged alternately on the bottom of the trenches and on the main area between adjacent trenches.
Second memory cells comprise MOS transistors which are vertical with respect to the main area and are each realized on the side walls of the trenches.
The first memory cells and the second memory cells differ with regard to the technological implementation of the MOS transistor. With regard to the storage capabilities, however, the first memory cells and the second memory cells are equivalent.
In accordance with the invention it is possible to program the memory cell configuration during the production of the memory cell configuration by producing the MOS transistors with different threshold voltages. This preferably takes place by means of masked channel implantation, in which the doping is deliberately changed in the channel region of the MOS transistors.
As an alternative, different threshold voltages of the MOS transistors are realized by virtue of the fact that the MOS transistors have gate dielectrics of different thickness depending on the stored information. In this case, use is made of the fact that when the thickness of the gate dielectrics differ by a factor of 10 or more, the threshold voltages of the MOS transistors differ from one another so distinctly that when a selection signal having a level between the two threshold voltages is applied, one MOS
Hofmann Franz
Krautschneider Wolfgang
Roesner Wolfgang
Elms Richard
Greenberg Laurence A.
Infineon - Technologies AG
Lebentratt Michael S.
Lerner Herbert L.
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