Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-06-20
2004-07-13
Nguyen, Ha Tran (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S612000, C438S617000, C438S618000, C385S014000
Reexamination Certificate
active
06762119
ABSTRACT:
FIELD OF THE INVENTION
The present disclosure relates generally to optoelectronic devices mounted on a silicon optical bench (SiOB). More particularly, the present invention relates to a package and method for fabricating semiconductor circuits containing an optical assembly while passively maintaining the alignment of the optical assembly.
BACKGROUND OF THE INVENTION
In the realm of optoelectronics, packaging has become a factor in the ability to manufacture reliable optoelectronic devices and systems. Passive alignment of a device and the subsequent packaging of the device assures the ability to mass produce devices and systems as well as to manufacture systems and devices at as low a cost as is possible. Of course, the packaging and passive alignment of devices and systems requires a great deal of precision in order to meet the required performance characteristic. To this end, while active alignment and packaging of devices offers precision in the alignment of the device and subsequent packaging, the attendant costs in packaging, as well as the inability to produce a large quantity of devices and systems has lead to the need for a package which is precisely aligned in a passive manner.
One area of technology which holds great promise in the realm of packaging optoelectronic devices and the passive alignment of both active and passive devices in an optoelectronic system is silicon waferboard technology. In addition to its utility as a physical support, silicon provides electronics capabilities, and is useful for forming and/or supporting passive optics (e.g., waveguides, etc.). Used in such a manner, silicon serves as an “optical bench.” Optical devices, systems and technology implemented in this manner are conventionally referred to as silicon optical bench (SiOB).
SiOB processing technology has advanced to the stage where a number of relatively simple procedures (e.g., oxidation, etching—isotropic or anisotropic) may be utilized to facilitate attachment of the devices to the support member, as well as alignment therebetween. Further, it is possible to form optical waveguiding structures directly in/on a silicon substrate, resulting in the ability to form a completely operable optical subassembly in silicon.
In general, utilization of silicon in the formation of a subassembly for optoelectronic devices includes a semiconductor (e.g., silicon) base and lid including a variety of etched features (e.g., grooves, cavities, alignment detents) and metallization patterns (e.g., contacts, reflectors) which enable the optoelectronic device to be reliably and inexpensively mounted on the base and coupled to a communicating optical fiber. In particular, an arrangement wherein the optoelectronic device (e.g., LED, laser diode, or photoelectric device) is disposed within a cavity formed by a lid member and the communicating fiber is positioned along a groove formed in a base member. A reflective metallization is utilized to optically couple the device to the fiber. Therefore, positioning of the device over the reflector is the only active alignment step required to provide coupling. Any remaining alignments are accomplished utilizing fiducial features formed in the base and lid members.
The assembled SiOB is typically a module for high speed switching of optical data. For reasons of contamination standard microelectronics joining, using BGA's or CGA's. and cleaning steps are not desirable. In addition, alignment accuracy is more critical between various light transmitting/receiving devices (i.e., 2-4 microns) compared with the conventional tolerance used in joining silicon chips to a chip carrier (e.g., 15-30 microns). In view of the above concerns, optical switch modules are presently wire bonded to cards. Wire bonding requires a costly manual process and leads to longer wiring paths. Furthermore, laser diodes and photo diodes are presently available with wire bond termination only.
Accordingly, what is desired is a less complex assembly for mounting the optical subassembly on a single material and in a smaller package thereby reducing the costs of not only the material, but also the complexity of the fabrication and thereby the cost of the assembly, while maximizing operating performance. There is also a need to allow both wire bond attachment of optical devices, as well as solderable metallurgy on a SiOB for attaching to a chip carrier.
BRIEF SUMMARY OF THE INVENTION
A process of forming an optical subassembly in an integrated circuit, the process comprising: defining electrically conducting lines and bonding pads in a metallization layer on a substrate; depositing a passivation layer over the metallization layer; etching the passivation layer to remove the passivation layer from each of the bonding pads and a portion of the metallization layer associated with each of the bonding pads; diffusing Cr from the lines proximate said bonding pads to prevent solder wetting down lines; bonding an optical device to one of the bonding pads; and attaching the substrate to a carrier utilizing solder bond attachment.
An interconnect structure for an optical subassembly is also disclosed, the optical subassembly comprising: a carrier having a first side and a second side; a ball grid array (BGA) depending from the second side; a cavity disposed in the first side, a silicon optical bench (SiOB) having an optical device mounted thereon, the SiOB is electrically and mechanically connected to the first side utilizing a surface mount technology (SMT) attachment, the cavity providing clearance for the optical device when connecting the SiOB to the carrier, the SiOB having a metallization layer providing both wire bondable and solder bondable pads.
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IEEE 1997; W. Pittroff, J. Barnikow, A. Klein, P. Kurpas, U. Merkel, K. Vogel & J. Wurfl, Electronic Components and Technology Conference “Flip Chip Mounting of Laser Diodes with Au/Sn Solder Bumps; Bumping, Self-Alignment and Laser Behavior”, pp. 1235-1241.
Cohen Mitchell S.
Herron Lester Wynn
Interrante Mario J.
Lombardi Thomas E.
Ray Sudipta K.
Cantor & Colburn LLP
International Bussiness Machines Corporation
Nguyen Ha Tran
Townsend Tiffany
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