Method of preventing resist poisoning in dual damascene...

Details Method of preventing resist poisoning in dual damascene... Method of preventing resist poisoning in dual damascene...

2005-11-29

2005-11-29

Nhu, David (Department: 2818)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S700000, C438S639000

Reexamination Certificate

active

06969683

ABSTRACT:
A method for forming a dual damascene interconnect in a dielectric layer is provided. Generally, a first aperture is etched in the dielectric. A poison barrier layer is formed over part of the dielectric, which prevents resist poisoning. A patterned mask is formed over the poison barrier layer. A second aperture is etched into the dielectric layer, wherein at least part of the first aperture shares the same area as at least part of the second aperture.

REFERENCES:
patent: 6436824 (2002-08-01), Chooi et al.
patent: 6482755 (2002-11-01), Ngo et al.
patent: 6528884 (2003-03-01), Lopatin et al.
patent: 6713386 (2004-03-01), Hu et al.

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