Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-03-13
2002-08-27
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S309000, C438S595000, C438S655000, C438S660000, C438S663000, C438S682000, C438S712000
Reexamination Certificate
active
06440809
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the invention
The present invention relates to a method of preventing ionic penetration into a gate oxide, more specifically, a method of preventing fluorine ions from residing in a gate to result in boron ion penetration into a gate oxide.
2. Description of the Prior Art
A metal-oxide semiconductor (MOS) is a very common electrical device in integrated circuits. A gate, a source, and a drain together comprise the MOS transistor to form a unit with four nodes. By utilizing channel effects generated by the gate of the MOS under different gate voltages, the MOS is often made to function as a digital solid switch. Both increasing complexity and precision in the development of integrated circuits has made controlling the manufacturing process of MOS transistors an important issue.
Please refer to
FIG. 1
to
FIG. 5
of the cross-sectional views of forming a MOS transistor according to the prior art. As shown in
FIG. 1
, a semiconductor wafer
10
has an oxide layer
14
, a conductive layer
16
, and an anti-reflection coating (ARC)
18
composed of silicon-oxy-nitride (SiO
x
N
y
) and formed by a plasma-enhanced chemical vapor deposition (PECVD) process positioned, respectively, on a substrate
10
.
As shown in
FIG. 2
, a patterned photoresist layer
20
is formed in a predetermined area on the ARC
18
to define patterns of a gate
22
. As shown in
FIG. 3
, an etching process is performed to remove portions of both the ARC
18
and the conductive layer
16
uncovered by the photoresist layer
20
. The gate
22
and the gate oxide layer
24
, composed of the remaining portions of the conductive layer
16
and the oxide layer
14
respectively, are thus formed on the surface of the substrate
12
.
As shown in
FIG. 4
, after stripping both the photoresist layer
20
and the ARC
18
, a first ion implantation process is performed using the gate
22
as a hard mask and boron fluoride (BF
2
+
) as the dopant to form lightly doped drains (LDD)
26
of the MOS transistor in the substrate
12
adjacent to the gate
22
. A spacer
27
is then formed around the gate
22
.
Finally, as shown in
FIG. 5
, a second ion implantation is performed using the gate
22
and the spacer
27
as a hard mask and boron (B) as the dopant to form a source
28
and a drain
29
of the MOS transistor in the substrate
12
adjacent to the spacer
27
.
However, when the first ion implantation process is performed using the gate
22
as a hard mask and boron fluoride (BF
2
+
) as the dopant to form the LDD
26
of the MOS transistor in the substrate
12
adjacent to the gate
22
, fluorine ions can easily penetrate into the gate
22
. In the subsequent second ion implantation process, the boron ions also penetrate into the gate
22
. Thus, threshold voltage change, leakage current, and capacitance-voltage curve distortion due to boron ion penetration into the gate oxide layer
24
, are enhanced by the fluorine ions that have previously penetrated into the gate
22
so as to cause a defect in the MOS transistor.
SUMMARY OF THE INVENTION
It is therefore a primary object of the present invention to provide a method of preventing fluorine ions from residing in a gate to result in boron ion penetration into a gate oxide.
In the preferred embodiment of the present invention, a substrate, an oxide layer, a conductive layer, an anti-reflection coating (ARC), and a photoresist layer defining patterns of a gate are formed, respectively, on a semiconductor wafer. An etching process is performed to remove portions of both the ARC and the conductive layer uncovered by the photoresist layer to form the gate and a gate oxide layer composed of the residual conductive layer and the oxide layer, respectively. After the photoresist layer is stripped, an ion implantation process is performed using the gate covered by the ARC as hard mask and boron fluoride (BF
2
+
) as the dopant to form lightly doped drains (LDD) in the substrate adjacent the gate. After the ARC is removed, a spacer is formed around the gate. Finally, the method is completed with the formation of a source and a drain in the substrate adjacent to the spacer after the ARC is stripped.
It is an advantage of the present invention against the prior art that the LDD of the MOS transistor is formed by performing the first ion implantation process, using instead the gate covered by the ARC as a hard mask and boron fluoride (BF
2
+
) as the dopant. Therefore, fluorine ion penetration, leading to boron ion penetration into the gate oxide and causing threshold voltage change, leakage current, and capacitance-voltage curve distortion, are prevented.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the multiple figures and drawings.
REFERENCES:
patent: 6013569 (2000-01-01), Lur et al.
patent: 6228757 (2001-05-01), Sengupta et al.
patent: 6238988 (2001-05-01), Hsiao et al.
patent: 2001/0034136 (2001-10-01), Kim et al.
Elms Richard
Hsu Winston
Luu Pho M.
United Microelectronics Corp.
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