Method of planarizing the semiconductor structure

Details Method of planarizing the semiconductor structure Method of planarizing the semiconductor structure

1997-04-30

1999-10-05

Chaudhari, Chandra

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Utilizing reflow

438762, 438633, 438763, 438698, 438699, H01L 2102

Patent

active

059638370

ABSTRACT:
A method for planarizing a semiconductor structure having a first surface region with a high aspect ratio topography and a second surface region with a low aspect ratio topography. A flowable material is deposited over the first and second surface regions of the structure. A portion of the material fills gaps in the high aspect ratio topography to form a substantially planar surface over the high aspect ratio topography. A doped layer, for example phosphorus doped glass, is formed over the flowable oxide material. The doped layer is disposed over the high aspect ratio and over the low aspect ratio regions. Upper surface portions over the low aspect ratio region are higher than an upper surface of the flowable material. The upper portion of the doped layer is removed over both the first and second surface portions to form a layer with a substantially planar surface above both the high aspect ratio region and the low aspect ratio region. The method is used for filling gaps, such as gaps between adjacent gate electrodes formed in a gate electrode surface region of a semiconductor structure.

REFERENCES:
patent: 5204288 (1993-04-01), Marks et al.
patent: 5268333 (1993-12-01), Lee et al.
patent: 5312512 (1994-05-01), Allman et al.
patent: 5449314 (1995-09-01), Meikle et al.
patent: 5534731 (1996-07-01), Cheung

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