Method of planarizing memory cells

Details Method of planarizing memory cells Method of planarizing memory cells

1996-12-10

1998-12-22

Tsai, Jey

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438250, H01L 218242

Patent

active

058518746

ABSTRACT:
A planarzation process is crucial for submicron VLSI or ULSI fabrication, The method of the present invention comprises forming a stacked capacitor contact on a substrate, forming a first dielectric layer on the capacitor contact. Next an etching process is performed to etchback the first dielectric layer. Finally, a second dielectric layer is formed on the first dielectric layer. A thermal reflowing may be also used to increase the planarization.

REFERENCES:
patent: 5393691 (1995-02-01), Hsu et al.
patent: 5618749 (1997-04-01), Takahashi et al.

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