Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
1998-05-11
2003-07-15
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
Reexamination Certificate
active
06593241
ABSTRACT:
BRIEF DESCRIPTION OF THE INVENTION
This invention relates generally to fabrication of semiconductor devices. More particularly, the invention relates to a method for planarizing a layer of material on a semiconductor device using a high density plasma system.
BACKGROUND OF THE INVENTION
Manufacturing of integrated circuits is becoming increasingly complex as the device density in such circuits increases. Highly dense circuits require closely spaced metal interconnect lines or features and multiple layers of materials and structures, all in micron and sub-micron dimensions. The surface of the layer will have a topography which generally conforms to the sublayer. The prior structures and layers create surface topography with areas of irregular elevation, troughs and the like. As the layers increase, the irregularities become more pronounced. Such topography adversely effects the fine pattern resolution and depth-of-focus limitations required for lithography, deposition of films, etching of interconnect lines and the overall yield and performance of the integrated circuit. Consequently it is desirable to planarize the layers to minimize such irregularities in the topography of the surface.
Planarization is a process used to create smooth, planar layers on wafers. There are two types of planarization required in the fabrication of semiconductors with multiple levels of metal interconnects; namely local and global planarization. Local planarization involves planarizing a dielectric film or layer deposited over dense arrays of interconnect metals. Global planarization is where the dielectric layer over the whole wafer is planarized.
For global planarization, Chemical Mechanical Polishing (CMP) is the most commonly used technique of planarization which essentially provides for polishing a wafer by rubbing a polishing pad against the wafer to grind the surface layer. Often, the polishing pad is saturated with an abrasive slurry solution which may aid the planarization. A commonly used slurry is colloidal silica in an aqueous KOH solution. CMP tools are well known in the art. The tools include a polishing wheel with the wafer attached. As the wheel rotates the wafer is forced against a wetted polishing surface and the surface of the wafer is planarized.
CMP has a number of limitations. It is a separate step requiring dedicated, and often times costly, equipment. There is no way to measure film removal rate during CMP. CMP rate and uniformity are influenced by pad conditions and pressure on the wafer. Additionally, the total planarization achievable with CMP is limited in terms of the step height of the metal interconnects or features. As device geometries shrink the demands on global planarization increase due to decreasing depth of focus of lithography steppers used to achieve such small geometries.
It has recently been found that high density plasma (HDP) chemical vapor deposition (CVD) processes used to deposit dielectric films such as gap fill oxides, and other layers, can be used in an attempt to achieve planar layers. One such method is described in U.S. Pat. No. 5,494,854. The '854 patent discloses the steps of depositing a HDP silicon dioxide gap fill dielectric layer over conductors to planarized high aspect ratio conductors, but the method does not necessarily planarize low aspect ratio conductors. A sacrificial polish layer is then deposited and a CMP process is used to planarize this sacrificial layer.
The '854 patent requires the use of a CMP process to complete the planarization process. As described above, the CMP process has limitations, and increases costs associated with performing this additional, independent step. Thus, it is desirable to provide an improved method of planarizing a layer of material on a semiconductor device or wafer that provides a planar layer and overcomes the aforementioned limitations. Specifically it is desirable to provide a method of planarizing that does not require additional steps and/or equipment such as CMP and spin on glass techniques, but is capable of providing in-situ planarizing.
OBJECTS AND SUMMARY OF THE INVENTION
Accordingly, it is an object of this invention to provide an improved method for planarizing a layer of material on a semiconductor device.
More particularly, it is an object of the present invention to provide an in-situ method for planarizing a layer on a semiconductor device using a high density plasma system.
Another object of the present invention is to provide a method of planarizing a layer using a sacrificial layer having a desirable etch rate difference compared to the gap fill layer.
A further object herein is to provide a method for planarizing a layer which can be easily incorporated into the semiconductor fabrication process.
Yet another objective of the present invention is to provide a planarization method capable of achieving both local and global planarization.
These and other objects are achieved by the method herein disclosed of forming a planar layer on a semiconductor device, having interconnect features, in a high density plasma CVD reactor which has a wafer support that may be biased by applying rf bias to provide sputter etching. The method comprises the steps of: depositing a gap fill oxide layer atop the interconnect features and substrate wherein angled facets are formed in the gap fill oxide above the interconnect features. Next, a sacrificial layer is deposited atop the gap fill oxide layer. The sacrificial layer has an etch to deposition ratio that is equal to or greater than the gap fill oxide at a given rf bias, and during this second depositing step the angled facets are etched at a rate greater than the rest of the layer, thereby causing the facets to substantially recede. The sacrificial layer is then etched to substantially remove the sacrificial layer and provides a substantially planar layer with a device specific thickness over the underlying metal. In one embodiment the sacrificial layer is sputter etched by a suitable sputter etching species or a combination of sputter etching species. In a second embodiment, the sacrificial layer is etched using a combination of sputter etching and chemical etching with a suitable sputter etching species, and a chemical etchant, respectively.
In an alternative embodiment, a “topcoat” may be deposited atop the semiconductor device after the sacrificial layer is etched to provide further planarization.
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Abraham Thomas
Bondur James Allan
Garcia James Paul
Anderson Matthew
Applied Materials Inc.
Moser Patterson & Sheridan
Utech Benjamin L.
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