Method of planarization using dummy leads

Details Method of planarization using dummy leads Method of planarization using dummy leads

1999-02-05

2000-12-05

Niebling, John F.

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

438691, 438612, 438742, 438743, 438744, H01L 2144, H01L 21461

Patent

active

061566608

ABSTRACT:
An Integrated Circuit Design which adds, to the standard conducting lines of the bulk metal layer, a pattern of a support structure which supports subsequent deposition in such a way that it eliminates previously experienced concavity or dishing of the subsequent deposition within areas which have a low density or absence of conducting lines. The dummy pattern enhances the deposition of filler material between conducting lines of the Integrated Circuit such that planarization of the bulk metal results in a smoother surface of the areas of the signal lines of the integrated circuit and within large open areas. Concurrently the present invention provides a means of successfully collecting data that are needed for Damascene processing.

REFERENCES:
patent: 5593903 (1997-01-01), Beckenbaugh et al.
patent: 5696406 (1997-12-01), Ueno
patent: 5700735 (1997-12-01), Shiue et al.
patent: 5707894 (1998-01-01), Hsiao
patent: 5911110 (1999-06-01), Yu

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