Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-10-20
2001-12-11
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S197000, C438S200000, C438S279000, C438S302000, C438S306000, C438S305000, C257S408000
Reexamination Certificate
active
06329235
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of performing a pocket implantation on a metal-oxide semiconductor (MOS) transistor, and more particularly, to a method of performing a pocket implantation on a MOS transistor for a memory cell of a dynamic random access memory (DRAM).
2. Description of the Prior Art
In the formation of DRAM, the gate width of the MOS transistor that serves as the pass transistor of the memory cell continues to shrink to increase the integration of the semiconductor wafer and enhance the reading rate of memory data. Recently, the DRAM fabrication process has begun to employ a pocket implantation (halo implantation) process to adjust the punch-through voltage of the pass transistor to prevent punch-through between the source and the drain of the pass transistor. The pocket implantation process forms two pocket doped regions in the silicon substrate below the lightly doped drain (LDD) or below the source and the drain to prevent punch-through between the source and drain. The pocket doped regions also lower the carrier concentration in the PN junction between the silicon substrate and the bottom layer of the source and drain, which reduces the PN junction capacitance and thereby enhances the operational rate of the MOS transistor.
Please refer to FIG.
1
and FIG.
2
.
FIG. 1
is a top view of a transistor
14
of a memory cell
12
of a DRAM
10
according to the prior art.
FIG. 2
is a sectional view along line
2
—
2
of the memory cell
12
of the DRAM
10
shown in FIG.
1
. The DRAM
10
is formed on a predetermined area of a semiconductor wafer and comprises a plurality of memory cells
12
arranged in a matrix format on the predetermined area.
Each of the memory cells
12
of the DRAM
10
comprises a capacitor to store electrical charge, and an N-type MOS (NMOS) transistor
14
electrically connected with a lower storage node
16
of the capacitor. Each NMOS
14
serves as a pass transistor for the memory cell
12
, and comprises a substrate
18
, a gate electrode layer
20
with a rectangular vertical cross section positioned on the substrate
18
along a predetermined direction, two spacers
22
positioned on the substrate
18
along two opposite side walls of the gate electrode layer
20
, two lightly doped layers
24
positioned on the surface of the substrate
18
below the two spacers
22
of two adjacent gate electrode layers
20
, and two heavily doped layers positioned on the surface of the substrate
18
next to the two opposite side walls of the gate electrode layer
20
and not covered by the two spacers
22
. The lightly doped layer
24
and the heavily doped layer act as the LDD and the source/drain
26
of the NMOS
14
, respectively. A contact hole
28
is formed between the partial side walls of the spacer
22
of two adjacent NMOS
14
and above the source/drain
26
, then the lower storage node
16
is formed inside the contact hole
28
above the source/drain
26
. The substrate
18
comprises a doped region
38
be low and around the source/drain
26
.
Please refer to FIG.
3
.
FIG. 3
is a schematic diagram of the formation of the doped region
38
below the NMOS
14
shown in FIG.
1
and FIG.
2
. The doped region
38
is formed by a pocket implantation process after forming the NMOS
14
. The pocket implantation process according to the prior art is performed by carrying on ion implantation processes in four different implanting directions. First, an ion implantation process implants ions into the substrate
18
along a specified direction
30
at a predetermined tilt angle &thgr;
P
. Then, the ion implantation process implants ions along the specified directions
32
,
34
and
36
in sequence at the same tilt angle &thgr;
P
to complete the pocket implantation region
38
. In
FIG. 3
, four dotted lines
31
a,
33
a,
35
a
and
37
a
are parallel with the surface of the substrate
18
, four dotted lines
31
b,
33
b,
35
b
and
37
b
are vertical to the surface of the substrate
18
, and the arrows
30
,
32
,
34
and
36
indicate four implanting directions at the predetermined tilt angle &thgr;
P
in the pocket implantation process according to the prior art.
The pocket implantation process according to the prior art repeats the ion implantation process in four implanting directions in the region between two adjacent gate electrode layers
20
, which results in a considerably high carrier concentration in the surface layer of the substrate
18
below that region, especially below the contact hole
28
. The repetitive ion implantation processes may destroy the crystalline structure in the surface layer of the substrate
18
, and the high carrier concentration increases the storage node junction electric field, which increases the junction leakage current. This higher leakage current can cause a more rapid loss of charge in the capacitor, which may adversely effect storage charge refresh times, or even cause mistakes in stored data.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide a method of performing a pocket implantation on a MOS transistor of a memory cell of a DRAM to solve the problem of high carrier concentrations between the gate conductive layer due to repetitive ion implantation processes.
In a preferred embodiment, the present invention provides a method of performing a pocket implantation on a MOS transistor of a memory cell of a DRAM. The DRAM is formed on a predetermined area of a semiconductor wafer and comprises a plurality of memory cells arranged in a matrix format on the predetermined area. Each of the memory cells comprises a transistor which comprises a substrate, a gate electrode layer with a rectangular vertical cross section positioned on the substrate, two spacers positioned on two opposite side walls of the gate electrode layer, two lightly doped layers positioned on the surface of the substrate below the two spacers, and two heavily doped layers positioned on the surface of the substrate next to the two opposite side walls of the gate electrode layer and not covered by the two spacers. The method comprises:
performing a first ion implantation process to implant ions into a region below one of the two lightly doped layers in a first direction to form a first pocket implantation region; and
performing a second ion implantation process to implant ions into a region below the other lightly doped layer in a second direction to form a second pocket implantation region;
wherein the angle between the first direction and the surface of the semiconductor wafer is the same as the angle between the second direction and the surface of the semiconductor wafer, and the horizontal direction projected from the first direction over the surface of the semiconductor wafer is opposite to that of the second direction.
It is an advantage of the present invention that the method is self-aligning and selective to maintain completeness of the crystalline structure and to maintain carrier concentrations below the contact hole of the lower storage node.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment which is illustrated in the various figures and drawings.
REFERENCES:
patent: 5998284 (1999-12-01), Azuma
patent: 6008080 (1999-12-01), Chuang et al.
patent: 6174778 (2001-06-01), Chen et al.
Hori et al., High-Performance Dual -Gate CMOS Utilizing a Novel Self-Aligned Pocket Implantation (SPI) Technology., IEEE Transactions On Electron Devices. vol. 40, No. 9, Sep. 1993.
Everhart Caridad
Hsu Winston
Keshavan Belur V
United Microelectronics Corp.
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