Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2000-07-13
2001-10-23
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S424000, C438S426000, C438S435000
Reexamination Certificate
active
06306741
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to methods of forming semiconductor devices and specifically to methods of defining poly gate electrodes and forming ultra-thin buffer oxide layers below the SiN gate dielectric in semiconductor device fabrication.
BACKGROUND OF THE INVENTION
Current processes for defining polysilicon (poly) gate electrodes involve the patterning of the gate through photolithography followed by an anisotropic poly etch which stops on the nitride (silicon nitride (SiN)) gate dielectric. However, etch selectivity between poly and nitride is poor hence stopping on the thin nitride gate dielectric becomes a significant problem. Poly edge GOI (gate oxide integrity) may become a problem if trenching of the silicon substrate occurs at the poly edge.
U.S. Pat. No. 5,963,818 to Kao et al. describes a method for forming an integrated circuit involves forming trench isolation regions and a damascene gate electrode region simultaneous with one another by over-lapping process steps using, inter alia, an inverse poly gate CMP.
U.S. Pat. No. 5,960,270 to Misra et al. describes a method for forming a metal gate MOS transistor using an inverse poly gate CMP. Source and drain regions are formed within a substrate self-aligned to a lithographically-patterned feature. The patterned feature is then removed and replaced by a metallic gate layer that is chemically mechanically polished (CMP) to form a metallic plug region that is either an inlaid or dual inlaid. The metallic plug region is self-aligned to the source and drain regions and preferably functions as a metal MOS gate region.
U.S. Pat. No. 5,943,576 to Kapoor describes a method of forming a MOS transistor having a narrow diffusion region that is smaller than the diffusion region defined using photoresist in a conventional CMOS processing. The method includes an inverse poly gate with sidewall spacers process.
U.S. Pat. No. 5,899,719 to Hong describes a method for making an FET (field effect transistor) having narrower gate electrodes and forming source/drain regions, including halo implants, in a more controlled manner. The method includes an inverse poly gate with sidewall spacers process.
U.S. Pat. No. 5,872,038 to Duane et al. describes a process for forming a semiconductor device having an elevated active region. A plurality of gate electrodes is formed on the semiconductor substrate an a thick oxide layer is disposed over the gate electrodes. A trench is formed in the thick oxide layer and is filled with a polysilicon material that is later doped to form an elevated active region above an active region of the substrate. The process includes a plain inverse poly gate CMP process.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a highly selective etch process for conductive gate patterning on thin gate dielectrics.
Another object of the present invention is to provide a method of defining conductive gate electrodes using a poly CMP instead of a plasma etch to reduce the total amount of plasma damage experienced by the gate dielectric.
Yet another object of the present invention is to provide a method of defining conductive gate electrodes that may result in improved PID (proportional integral derivative) immunity.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a silicon substrate having at least one active area is provided. A buffer layer overlies the silicon substrate and a gate dielectric layer overlies the buffer layer. A sacrificial oxide layer is formed over the gate dielectric layer. A nitride layer is formed over the sacrificial oxide layer. The nitride layer is patterned to form an opening therein within the active area exposing a portion of the sacrificial oxide layer within the opening. The portion of the sacrificial oxide layer within the opening is stripped, exposing a portion of the underlying gate dielectric layer within the opening. A gate electrode is formed within opening over the portion of the gate dielectric layer. The remaining nitride layer is selectively removed. The remaining sacrificial oxide layer is then stripped and removed.
REFERENCES:
patent: 5872038 (1999-02-01), Duane et al.
patent: 5899719 (1999-05-01), Hong
patent: 5943576 (1999-08-01), Kagoor
patent: 5960270 (1999-09-01), Misra et al.
patent: 5963818 (1999-10-01), Kao et al.
patent: 6087243 (2000-07-01), Wang
Lee James Yong Meng
Li Xia
Zhang Yun Qiang
Berry Renee R.
Chartered Semiconductor Manufacturing Inc.
Nelms David
Pike Rosemary L. S.
Saile George O.
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