Method of patterning gate electrode with ultra-thin gate...

Details Method of patterning gate electrode with ultra-thin gate... Method of patterning gate electrode with ultra-thin gate...

2000-01-18

2002-11-05

Hiteshew, Felisa (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S710000, C438S712000, C438S720000

Reexamination Certificate

active

06475916

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of creating poly gate electrodes with ultra-thin gate oxide dielectrics.
(2) Description of the Prior Art
Recent advances in semiconductor fabrication have resulted in significant decreases in device feature size and increase in device density thereby increasing device performance to a considerable degree. One of the frequently used devices in Ultra Large Scale Integration (ULSI) technology is the Field Effect Transistor (FET) that consists of a polysilicon gate electrode with self aligned source and drain regions. The popularity of FET devices is in no small measure due to their high packaging, low power consumption and high yields.
Conventional gate electrodes are fabricated by first growing a thin layer of gate oxide on the surface of a single crystalline semiconductor substrate. To reduce short channel effects that are caused by ultra-short device feature size, Lightly Doped Drain (LDD) regions are implanted into the surface of the substrate in addition to the implantation of source and drain regions. The channel length of a FET device is the distance under the gate electrode between the source and the drain contacts. For the creation of a typical gate electrode, a layer of polysilicon is deposited over a layer of gate oxide and etched using photolithography followed by anisotropic poly etch. The anisotropic poly etch typically stops on the gate oxide, for applications where the layer of gate oxide is very thin this etch stop can easily become a problem resulting in the etch for the poly gate proceeding into the underlying substrate. The invention addresses this problem.
The current method of fabricating MOSFET devices is briefly highlighted using
FIGS. 1
a
through
1
d.
FIG. 1
a
shows how the process of fabrication starts with a single crystal semiconductor substrate
10
that has been provided with a level of conductivity by doping the substrate with for instance a p-type impurity such as boron or indium forming a p-type well in the surface of the substrate. The active surface of the substrate in which the gate electrode is to be created is electrically isolated by the creation of the Field Oxide (FOX) or STI regions
14
. A thin layer
12
of gate oxide is next grown over the active region in the surface of the substrate
10
, a layer
16
of polysilicon is deposited and patterned to form the gate electrode. To offset the previously mentioned short channel effect, the LDD regions
18
are implanted (
17
) using a (in view of the p-type well) n-type impurity such as arsenic or phosphorous.
FIG. 1
b
shows the next step in the creation of the gate electrode, that is the creation of gate spacers that electrically isolate the gate electrode. For this purpose, a layer
20
of gate spacer material, such as silicon dioxide, is deposited as shown in
FIG. 1
b
, that is over the surface of the gate electrode and its surrounding substrate including the surface of the FOX regions. The implanted ions of the LDD can at this time be further driven into the surface of the substrate by heating the substrate to a temperature of between 700 and 900 degrees C., a process that at the same time restores any damage to the surface of the substrate that the LDD ion implant may have caused. The gate spacer material that has been deposited must next be etched back from all regions others than the sidewalls of the gate electrode, this is achieved by applying an anisotropic dry etchback that removes most of the gate spacer material and only leaves gate spacer material in place where it was most densely deposited, that is on the sidewalls of the gate electrode. The gate spacers
22
,
FIG. 1
c
, have now been formed. The remaining step of forming the source
23
and
24
regions of the gate electrode is performed by the implant
26
,
FIG. 1
d
. This implant uses the same type impurity as has been used for the LDD implant but provides the implanted ions with higher dopant concentration and implant energy thereby creating deeper regions of impurity with higher concentration of these impurities.
It is clear that the process of creating MOSFET devices is relatively complicated and that the concurrent reduction in device feature size can readily lead to interaction of ion concentrations in closely spaced regions. For instance, the relatively low-energy LDD implant ions can readily interact with the sidewalls of the gate electrode during the implant causing non-uniform implant of the ions in the LDD regions. These uneven implants can create dense spots of ion concentrations in the LDD regions leading to leakage currents. It is also important that the LDD implant is correctly aligned with the gate electrode so as to avoid gaps between the LDD regions in the surface of the substrate and the gate electrode. This gap can lead to variations in the device threshold performance characteristics and can cause reliability concerns. It is further important that the surface of the substrate is not affected by the etch that is applied to create the gate electrode. Damage to the surface of the substrate causes increased leakage current over the surface of the substrate in addition to a non-uniform doping profile of the LDD and source/drain regions thereby increasing the standby current of the MOSFET. These effects and the elimination of these effects have received considerable attention in the field of semiconductor research and development. The present invention addresses the elimination of surface damage that can be caused to the surface of the substrate for sub-micron devices where a very thin layer of gate oxide is used as the stop layer for the gate electrode etch.
U.S. Pat. No. 5,786,256 (Gardner et al.) shows a gate opening in a SAC, SiN, and TEOS layer; form SiN spacer in gate opening; form thin gate oxide between spacers; form poly gate (inverse gate) between spacers using CMP. Note that Gardner specifies that the dielectric stack can have alternate compositions. See col. 5, lines 49 to 59. The are however major differences between Gardner et al. and the present invention, as follows:
the Gardner method is not optimized for gate oxide formation, especially for thin gate oxides that are less than 40 Angstrom
the process of gate spacer etch stops on the silicon substrate and therefore damages the substrate prior to the formation of the layer of gate oxide
the present invention addresses problems of gate oxide uniformity and reliability, these problems have not been addressed in the Gardner method of U.S. Pat. No. 5,786,256
the present invention uses a triple stack that surrounds the gate electrode. The top most layer of the stack is a layer of oxide that is used as etch stop for the gate spacer etch while the gate spacer of the invention is formed on top of the gate oxide and not on the surface of the substrate (as for Gardner), thus not damaging the substrate during spacer etch
the invention provides a method for growing gate oxide less than 20 angstrom thick, and
the invention uses nitride for spacer material.
U.S. Pat. No. 5,786,255 (Yeh et al.) shows an inverse gate process. Yeh appears to be similar with the instant invention and shows an inverse poly gate process with a thin gate oxide. One of the differences between Yeh et al. and the instant invention is that Yeh teaches the use of a silicon nitride layer for the definition of the poly gate that is the same as the silicon nitride that is used for the definition of the field isolation regions. The poly of the gate that is created in accordance with Yeh can therefore not be used as an interconnect while the poly of the gate of the invention extends beyond the field isolation regions and can therefore be used as an interconnect.
U.S. Pat. No. 5,817,560 (Gardner et al.), U.S. Pat. No. 5,472,894 (Hsu et al.), U.S. Pat. No. 5,766,998 (Tseng et al.) and U.S. Pat. No. 5,937,297 (Peidous) show other inverse gate processes (some with spacers).
U.S. Pat. No. 5,915,181 (Tseng) and U.S. Pat. No. 5,447

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