Data processing: generic control systems or specific application – Specific application – apparatus or process – Product assembly or manufacturing
Reexamination Certificate
1999-10-05
2002-11-19
Picard, Leo (Department: 2121)
Data processing: generic control systems or specific application
Specific application, apparatus or process
Product assembly or manufacturing
C700S108000, C700S121000, C438S014000
Reexamination Certificate
active
06484064
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to manufacturing semiconductor products, and, more particularly, to a method and apparatus for performing wafer standard routing for cross-fab metrology calibration.
2. Description Of The Related Art
The technology explosion in the manufacturing industry has resulted in many new and innovative manufacturing processes. Today's manufacturing processes, particularly semiconductor manufacturing processes, call for a large number of important steps. These process steps are usually vital, and therefore, require a number of inputs that are generally fine-tuned to maintain proper manufacturing control.
The manufacture of semiconductor devices requires a number of discrete process steps to create a packaged semiconductor device from raw semiconductor material. The various processes, from the initial growth of the semiconductor material, the slicing of the semiconductor crystal into individual wafers, the fabrication stages (etching, doping, ion implanting, or the like), to the packaging and final testing of the completed device, are so different from one another and specialized that the processes may be performed in different manufacturing locations that contain different control schemes.
Among the important aspects in semiconductor device manufacturing are RTA control, chemical-mechanical Planarization (CMP) control, and overlay control. Overlay is one of several important steps in the photolithography area of semiconductor manufacturing. Overlay control involves measuring the misalignment between two successive patterned layers on the surface of a semiconductor device. Generally, minimization of misalignment errors is important to ensure that the multiple layers of the semiconductor devices are connected and functional. As technology facilitates smaller critical dimensions for semiconductor devices, the need for reduced of misalignment errors increases dramatically.
Generally, photolithography engineers currently analyze the overlay errors a few times a month. The results from the analysis of the overlay errors are used to make updates to exposure tool settings manually. Some of the problems associated with the current methods include the fact that the exposure tool settings are only updated a few times a month. Furthermore, currently the exposure tool updates are performed manually.
Generally, a set of processing steps is performed on a lot of wafers on a semiconductor manufacturing tool called an exposure tool or a stepper. The manufacturing tool communicates with a manufacturing framework or a network of processing modules. The manufacturing tool is generally connected to an equipment interface. The equipment interface is connected to a machine interface to which the stepper is connected, thereby facilitating communications between the stepper and the manufacturing framework. The machine interface can generally be part of an advanced process control (APC) system. The APC system initiates a control script, which can be a software program that automatically retrieves the data needed to execute a manufacturing process. Often, semiconductor devices are staged through multiple manufacturing tools for multiple processes, generating data relating to the quality of the processed semiconductor devices. Many times, inaccuracies in manufacturing processes cannot be measured because they may involve a semiconductor process characteristic that may be difficult to measure. This could cause quality problems that may otherwise be corrected if data relating to the inaccuracies had been acquired.
Furthermore, wafers that are processed in different location may carry metrology data associated with each process that was performed on a particular semiconductor wafer. Many times, one set of data associated with a particular metrology tool will not properly correspond with data from another metrology tool from a different manufacturing area. This could cause inherent bias or drift in the measurements made on a semiconductor wafer as it is being processed through various manufacturing areas.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
In one aspect of the present invention, a method is provided for running metrology standard wafer routes for calibrating metrology data. A processing order for a run of semiconductor devices is determined. A metrology route based upon the processing order is determined. A metrology standard device is routed through the metrology route. Measurement data relating to the metrology standard device being routed though the metrology route is acquired. Metrology data processing upon the acquired measurement data is performed.
In another aspect of the present invention, an apparatus is provided for running metrology standard wafer routes for calibrating metrology data. The apparatus of the present invention comprises: means for determining a processing order for a run of semiconductor devices; means for determining a metrology route based upon the processing order; means for routing a metrology standard device through the metrology route; means for acquiring measurement data relating to the metrology standard device being routed though the metrology route; and means for performing metrology data processing upon the acquired measurement data.
REFERENCES:
patent: 5862055 (1999-01-01), Chen et al.
patent: 6255125 (2001-07-01), Schmidt et al.
patent: 6277658 (2001-08-01), Jeng et al.
patent: 6292708 (2001-09-01), Allen et al.
Advanced Micro Devices , Inc.
Garland Steven R.
Picard Leo
Williams Morgan & Amerson P.C.
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