Method of patterning gate electrode conductor with ultra-thin ga

Details Method of patterning gate electrode conductor with ultra-thin ga Method of patterning gate electrode conductor with ultra-thin ga

1999-12-20

2000-08-22

Smith, Matthew

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438265, 438197, 438585, 257288, 257332, H01L 21336

Patent

active

061071404

ABSTRACT:
A method of patterning a gate electrode comprising the following steps. A semiconductor structure, with an upper silicon layer, and having an active area is provided. A sacrificial oxide layer overlies the semiconductor structure, a first polysilicon layer overlies the sacrificial silicon oxide layer, and a silicon nitride layer overlies the polysilicon layer. The nitride, first poly, and sacrificial oxide layers are patterned to form a gate conductor opening within the active area. A gate oxide layer is grown over the semiconductor structure within the gate conductor opening an oxide sidewall spacers are grown on the first polysilicon sidewalls. A second polysilicon layer is deposited over the structure, filling the gate conductor opening. The second polysilicon layer is polished to remove the excess of the second polysilicon layer from the nitride layer, forming a polysilicon gate conductor within the gate conductor opening and over the gate oxide layer. The polysilicon gate conductor has an exposed upper surface that is oxidized to form a hard mask oxide layer over the polysilicon gate conductor. The nitride layer is etched and removed from the first polysilicon layer. The first polysilicon layer is etched and removed. The oxide sidewalls and hard mask are removed.

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