Method of optimizing interconnect distribution to improve...

Details Method of optimizing interconnect distribution to improve... Method of optimizing interconnect distribution to improve...

2005-10-27

2008-12-30

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07472367

ABSTRACT:
A method of distributing an array of interconnects on an electronic device divides the array into multiple regions, each region having certain performance requirements. For each region, predefined performance curves are used to choose from a plurality of interconnect distribution pattern modules one or more interconnect distribution pattern modules that satisfy the corresponding performance requirements. The chosen interconnect distribution pattern modules are used to generate a performance indication map highlighting those vulnerable interconnect(s) that may suffer severe crosstalk interference. Each vulnerable interconnect is then relocated to a different location until the performance requirements are met.

REFERENCES:
patent: 6523154 (2003-02-01), Cohn et al.
patent: 6789241 (2004-09-01), Anderson et al.
patent: 6915249 (2005-07-01), Sato et al.

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