Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-01-19
2001-02-13
Whitehead, Jr., Carl (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S638000, C438S687000, C257S760000
Reexamination Certificate
active
06187663
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to processes used to fabricate semiconductor devices, and more specifically to a process used to increase the performance of semiconductor device via use of more conductive metal structures, and lower dielectric constant, insulator layers.
(2) Description of the Prior Art
The continuing objectives of the semiconductor industry has been to increase the performance of semiconductor devices, while still maintaining, or reducing, the cost of these same semiconductor devices. The use of sub-micron features, or micro-miniaturization, used for semiconductor devices, has allowed the performance and cost objectives to be aggressively addressed. Devices with smaller features result in a reduction of performance degraded capacitances, evidenced by the higher performing metal oxide semiconductor field effect transistor, (MOSFET), devices, fabricated with sub-quarter micron channel lengths. In addition the use of sub-micron features result in a smaller semiconductor chip, however still possessing the same, or greater, device densities, than larger size semiconductor chips, fabricated using larger features. This allows more semiconductor chips to be realized from a specific size substrate, thus reducing the cost of a specific semiconductor chip.
Micro-miniaturization has in part, been accomplished via advances in specific semiconductor disciplines, such as photolithography, and dry etching. The use of more advanced exposure cameras, as well as the use of more sensitive photoresist materials, have allowed sub-micron images to be routinely achieved in photoresist layers. In addition, the development of more advanced dry etching tools, and processes, have allowed the sub-micron images, in overlying photoresist layers, to be successfully transferred to underlying conductive and insulating materials, used for the fabrication of semiconductor devices. However, in addition to the advances in semiconductor fabrication disciplines, specific structural developments, as well as material upgrades, are still needed to continue to improve device performance and lower cost.
The use of copper interconnect structures, exhibiting lower resistivity than aluminum, or tungsten counterparts, and the use of low dielectric constant, (low k), materials, such as hydrogen silsesquioxane, (HSG), or fluorinated silicate glass, (FSG), such as silicon oxyfluoride, have been used to decrease RC, (resistance—capacitance), delays. The more conductive copper interconnect structures, with increased electromigration resistance, compared to aluminum based counterparts, allow narrower metal interconnect structures to be used. However the definition of copper structures, using conventional photolithographic and dry etching procedures, can prove difficult when defining narrow metal interconnect structures, therefore the use of damascene metal structures, avoiding the difficulties encountered with conventional patterning procedures, has gained attention. This invention will describe a process in which a copper damascene structure, (single, or dual damascene), is embedded in a two level, composite insulator layer, with each component of the two level, composite insulator layer, having a low dielectric constant. The two levels of the composite insulator layer, are separated by a thin, silicon oxynitride layer, used as an etch stop layer, when forming the upper, wide diameter opening, of a dual damascene pattern, in the top level of composite insulator layer. In addition each level of the composite insulator layer, is comprised with two dielectric layers, each being a low k material. This is used to optimize capacitance, as well as to allow the use of an underlying HSQ layer, with a dielectric constant of about 2.8, to be integrated into the fabrication sequence, residing underlying a protective FSG layer, which in addition also features a low dielectric constant. Prior art, such as Fiordalice et al, in U.S. Pat. No. 5,578,523, as well as Lin, in U.S. Pat. No. 5,753,967, describe the use of low k dielectric constant layers, with a hard mask used between these layers. However those prior arts do not describe the use of two levels of low k dielectric constant layers, which each low k dielectric constant layer, a composite layer, comprised of two low k layers, each needed to achieve both capacitance objectives, as well as reducing fabrication complexities.
SUMMARY OF THE INVENTION
It is an object of this invention to improve the performance of a semiconductor device, via use of a copper damascene structure, and via the use of low k dielectric layers, used for passivation.
It is another object of this invention to use two levels, of composite insulator layers, to embed the copper damascene structure, with a wide diameter, copper interconnect shape, embedded in the top level of the two level, composite insulator layer, and with a narrow diameter, copper via structure, embedded in the bottom level of the two level, composite insulator layer.
It is still another object of this invention to use a composite insulator layer, for each level of the two level, composite insulator layer, comprised of an overlying, low k dielectric layer of fluorinated silicon glass, (FSG), and an underlying, low k dielectric layer of hydrogen silsesquioxane, (HSQ).
It is still yet another object of this invention to use a thin silicon oxynitride layer, between the levels of composite insulator layer, to serve as an etch stop for the patterning of the wide diameter, damascene opening, in the top level of the two level, composite insulator layer.
In accordance with the present invention a method of fabricating a copper damascene structure, in a low k, two level, composite insulator layer, is described. A first level, composite insulator layer, comprised of an overlying layer of FSG, and an underlying layer of HSQ, is formed on the top surface of an underlying insulator layer, as well as on the top surface of an lower level, metal interconnect structure, which is located in, or located on the underlying insulator layer. After deposition of a thin layer of silicon oxynitride, a second level, composite insulator layer, again comprised of an overlying FSG layer, and an underlying HSQ layer, is formed on the silicon oxynitride layer. A wide diameter opening, is next formed in the second level, composite insulator layer, via a selective, dry etching procedure, using the silicon oxynitride layer, as an etch stop. A narrow diameter opening is next formed, via dry etching procedures, in the silicon oxynitride layer, and in the first level, composite insulator layer, exposing a portion of the top surface of the lower level, metal interconnect structure. After deposition of a copper layer, completely filling the openings in the two level, composite insulator layer, unwanted regions of copper are removed from the top surface of the second level, composite insulator layer, resulting in a copper damascene structure, embedded in a low k, two level, composite insulator layer.
REFERENCES:
patent: 5578523 (1996-11-01), Fiordalice et al.
patent: 5741626 (1998-04-01), Jain et al.
patent: 5753967 (1998-05-01), Lin
patent: 5763010 (1998-06-01), Guo et al.
patent: 5767582 (1998-06-01), Lee et al.
patent: 6054769 (2000-04-01), Jeng
Chang Weng
Cheng Yao-Yi
Jang Syun-Ming
Yu Chen-Hua
Ackerman Stephen B.
Berezny Neal
Jr. Carl Whitehead
Saile George O.
Taiwan Semiconductor Manufacturing Company
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