Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-03-07
2006-03-07
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07010763
ABSTRACT:
Disclosed is a method for achieving timing closure in the design of a digital integrated circuit or system by selecting portions of the circuit or system to be optimized and portions of the circuit or system in which the effects of such optimization are to be analyzed during the optimization process. Optimized portions will include gates whose design parameters are to be changed, a first analyzed portion includes gates whose delays and edge slews are to be recomputed, and a second analyzed portion includes gates whose ATs and RATs are to be recomputed during optimization. Constraints are imposed at selected boundaries between these portions to prevent unwanted propagation of timing information and to ensure the validity of timing values used during optimization. Through this selection, the size of the problem posed to the underlying optimization method will be reduced, allowing larger circuits or systems to be optimized and allowing optimization to be performed more quickly.
REFERENCES:
patent: 5798658 (1998-08-01), Werking
patent: 6430731 (2002-08-01), Lee et al.
patent: 6721924 (2004-04-01), Patra et al.
Hathaway David J.
Lange Lawrence Kenneth
Visweswariah Chandramouli
Williams Patrick M.
Augspurger Lynn L.
Do Thuan
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