Method of operating a memory at high speed using a cycle...

Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing

Reexamination Certificate

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Details

C711S105000, C710S058000, C710S061000, C712S220000, C712S227000, C713S400000, C365S189011, C365S191000, C365S193000

Reexamination Certificate

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10663144

ABSTRACT:
A self-clocking memory device comprises a memory array, a memory input circuit, and a memory control circuit. The memory input circuit is operable to receive an input clock signal and generate a memory operation initiation signal in response thereto, while the memory control circuit is operable to receive the memory operation initiation signal and generate one or more control signals to initiate a memory operation in response thereto. The memory control circuit is further operable to identify completion of the memory operation and generate a cycle ready strobe signal in response thereto. The memory input circuit receives the cycle ready strobe signal as an input and generates a next memory operation initiation signal in response thereto for initiation of a next memory operation.

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patent: 2002/0157062 (2002-10-01), Greiner

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