Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2009-10-29
2011-12-06
Richards, N Drew (Department: 2895)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S197000, C438S404000, C438S594000
Reexamination Certificate
active
08071453
ABSTRACT:
A method of ONO integration of a non-volatile memory device (e.g. EEPROM, floating gate FLASH and SONOS) into a baseline MOS device (e.g. MOSFET) is described. In an embodiment the bottom two ONO layers are formed prior to forming the channel implants into the MOS device, and the top ONO layer is formed simultaneously with the gate oxide of the MOS device.
REFERENCES:
patent: 6946349 (2005-09-01), Lee et al.
patent: 2004/0110390 (2004-06-01), Takagi et al.
patent: 2006/0035432 (2006-02-01), Kim et al.
patent: 2009/0104780 (2009-04-01), Lee
Jenne Fredrick B.
Jin Bo
Ramkumar Krishnaswamy
Bradford Peter
Cypress Semiconductor Corporation
Richards N Drew
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