Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Recessed oxide by localized oxidation
Patent
1998-03-26
1999-10-19
Fourson, George
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Recessed oxide by localized oxidation
438452, 438439, H01L 21762
Patent
active
059703644
ABSTRACT:
A method for forming an isolation region in an integrated circuit is disclosed. The method includes forming a pad layer on a semiconductor substrate, and forming an oxidation masking layer on the pad layer, wherein the pad layer relieves stress from the oxidation masking layer. Next, portions of the oxidation masking layer and the pad layer are patterned and etched. A first oxide layer is thermally grown on the substrate, and a second oxide spacer is formed on a sidewall of the pad layer and the oxidation masking layer. After forming a nitride spacer on a surface of the second oxide spacer, the substrate is thermally oxidized to form the isolation region in the substrate.
REFERENCES:
patent: 4563227 (1986-01-01), Sakai et al.
Teng, C., et al., "Optimization of Sidewall Masked Isolation Process", IEEE Journal of Solid-State Circuits, vol. Sc-20, No. 1, pp. 44-51 Feb. 1985.
Hong Gary
Huang Hsiu-Wen
Fourson George
United Semiconductor Circuit Corp.
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