Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Optimization
Reexamination Certificate
2011-08-09
2011-08-09
Doan, Nghia M (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Optimization
C716S106000, C716S107000, C716S108000, C716S111000, C716S113000, C716S114000
Reexamination Certificate
active
07996812
ABSTRACT:
A system and a method for correcting early-mode timing violations that operate across the process space of a circuit design. Optimizations are performed to replace padding that increase path delays on fast paths. At the stage in the design process where early-mode violations are addressed, placement, late-mode timing closure, routing, and detailed electrical and timing analysis are assumed to have been completed. The optimizations are designed to be effective in delaying fast paths while minimizing the impact on already-completed work on the chip, in contrast to relying only on adding pads that can have a negative impact on all of these quantities. The optimizations are classified according to their invasiveness and are followed by their deployment. The deployment is designed to minimize using delay pads, reduce design disruptions, and minimize effects on other aspects of the design.
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Kotecha Pooja M.
Musante Frank J.
Pureswaran Veena S.
Trevillyan Louise H.
Villarrubia Paul G.
Doan Nghia M
International Business Machines - Corporation
Schnurmann H. Daniel
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